Serdes PHY - 1.25~5Gbps, compatible with SATAII, SAS, PCIe and SONET
IP
- Optical Transport
- Silicon Proven
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Serdes PHY - 1.25~5Gbps, compatible with SATAII, SAS, PCIe and SONET
IP
8 Channel Stand-alone CAN controller
The TEECAN8 is an IC targeted to industry applications using CAN.
In machine vision components, especially cameras, the standard GigE Vision has almost established.
USB 1.1.OTG PHY IP, OTG, UMC 90nm SP process
USB 1.1 OTG PHY, UMC 90nm SP/RVT Low-K Logic process.
USB 1.1.OTG PHY IP, OTG, UMC 65nm SP process
USB 1.1 On-The-Go PHY, UMC 65nm SP/HVT Logic Low-K process.
The USB1.1 PHY is an IP version of USB transceiver.
The XPS Universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides …
The USB11PHY is an IP version of USB transceiver.
The USB11PHY is an IP version of USB transceiver.
USB 2.0 OTG PHY IP, UMC 0.13um LL/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um LL process.
The USB 2.0 Host Controller provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB).
USB 1.1.OTG PHY IP, OTG, UMC 0.25um Logic process
USB 1.1 On-The-Go transceiver (ECN spec), UMC 0.25um Logic process.
SATA II PHY IP, Gen-2, 1 - port, UMC 0.18um G2 process
1.5G/3.0Gbps 1 port Serial ATA PHY and ESATA, UMC 0.18um GII Logic process.
LVDS Transmitter IP, Tx IO, UMC 55nm SP process
0.18um TX PAD, UMC 0.18um Logic RVT-FSG process.
USB 1.1.OTG PHY IP, OTG, UMC 0.15um SP process
USB 1.1 On-The-Go transceiver, UMC 0.15um SP Logic process.
USB 1.1 PHY IP, UMC 0.15um SP process
USB 1.1 PHY, UMC 0.15um SP Logic process.
USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process.
USB 1.1.OTG PHY IP, OTG, UMC 0.13um SP/FSG process
USB 1.1 On-The-Go transceiver, UMC 0.13um SP/FSG Logic process.
USB 1.1 PHY IP, UMC 0.13um HS/FSG process
USB 1.1 PHY, UMC 0.13um HS/FSG Logic process.
SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
Serial ATA (SATA) physical layer that provides a range of host and device functions, UMC 0.13um HS/FSG Logic process.