64-bit PCI-X Master/Target
- PCI
- now
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
64-bit PCI-X Master/Target
The host/device (OTG) solutions include a variety of host device configurations around a single USB port.
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
Single channel serial ATA PHY layer compliant with SATA spec.
USB 1.1.OTG PHY IP, OTG, UMC 0.18um G2 process
USB 1.1 On-The-Go transceiver (ECN spec), UMC 0.18um GII Logic process.
IP
Scan Ring Linker enables multiple 1149.1 scan rings
Scan Ring Linker enables multiple 1149.1 scan rings
AMBA AHB to PCI Host Bridge
AMBA AHB Bus Master
AMBA AHB Bus Slave
PCI-to-PCI Bridge
PCI-ISA Bridge
UART
PCI Bus Arbiter
64-bit PCI Host Bridge
64-bit PCI Bus Target
64-bit PCI Bus Master/Target
32-bit PCI Host Bridge
32-bit PCI Bus Target
32-bit PCI Bus Master/Target
PowerPC to PCI Bridge