USB4 Gen3 x2-lane PHY, TSMC N6, 1.8V or 1.2V, N/S orientation, type-C
The USB4 Gen3x2 transceiver IP provides a range of USB4 Gen3x2 host and peripheral applications up to 40Gbps.
- USB4
- TSMC
- 3nm
- N3X
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
USB4 Gen3 x2-lane PHY, TSMC N6, 1.8V or 1.2V, N/S orientation, type-C
The USB4 Gen3x2 transceiver IP provides a range of USB4 Gen3x2 host and peripheral applications up to 40Gbps.
USB4 Gen3 x2-lane PHY, TSMC N7, 1.8V or 1.2V, N/S orientation, type-C
The USB4 Gen3x2 transceiver IP provides a range of USB4 Gen3x2 host and peripheral applications up to 40Gbps.
USB4 Gen3 x2-lane PHY, TSMC 12FFC, 1.8V, N/S orientation, type-C
The USB4 Gen3x2 transceiver IP provides a range of USB4 Gen3x2 host and peripheral applications up to 40Gbps.
Get to market faster using our highly configurable network on chip
The 1G UDP Stack IP® enables efficient data transmission over the internet using the UDP protocol for low-latency, loss-tolerant …
The 10G UDP IP Stack offers a hardware protocol stack for efficient UDP/IP communication over LANs or point-to-point connections.
The 40G UDP IP Stack enables fast communication over LAN or point-to-point connections, even without a CPU, by handling UDP/IP en…
UCIe-S PHY for Standard Package (x32) in TSMC N3P, East/West Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
The CAN XL IP represents a breakthrough, bridging the gap between CAN FD and 100Mbit Ethernet.
PCIe 7.0 Switch with with Time Division Multiplexing
The PCI Express® (PCIe®) 7.0 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementati…
PCIe 7.0 Retimer Controller with CXL Support
PCI Express® (PCIe®) 7.0 links operating at 128 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions o…
The PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations.
The PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations.
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
The integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors,…
The I3C Target Lite is a configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivi…
Ultra-small footprint, static framing, DPTx 1.4 IP core
Ultra-small footprint, static framing, DPTx 1.4 IP core
PCIe 6.0 PHY, TSMC N6 x4 1.2V, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
MIPI A-PHY
LVDS I/O IP - High Frequency Transceiver
The Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data t…