Overview
To provide a solution to the MMC cards, SMIC18_MMC_03_4IN1 is consolidated by four independent IPs: SMIC18_PRG_03_33T18V60_240mA, SMIC18_ROSC_01_55M, SMIC18_VDT_01_1P5V2P3V and SMIC18_POR_03_1P8V. It can provide two regulated 1.8v output voltages, monitor the rising of supply voltage and detect the supply voltage. Also, an on chip ring oscillator is built in. To cut down the pin numbers and area, one V18F pin and one AVDDH pin have been removed. The total output current of V18F should not be over 160mA.
Learn more about Mixed Signal Subsystem IP core
Increasingly, product managers are considering a custom Analog SoC as an effective way to drastically reduce BOM costs. What would have been considered a radical product innovation just a few years ago, is now viewed as a viable route as even where product volumes are considered low NRE costs can in fact be recovered in short period of time. Innovative SoC solutions are challenging but the benefits are compelling where risk can be mitigated by choosing a development partner with a clear understanding of all the system components and of the various technology options for the SoC implementation. In a recently issued paper, S3 Group’s experts talk about the advantages of custom SoCs and build a strong business case for investment in a SoC development.
This paper describes the design & verification methodology used on a recent large mixed signal System on a Chip (SoCs) which contained radio frequency (RF), analog, mixed-signal and digital blocks on one chip. We combine a top-down functional approach, based on early system-level modelling, with a bottom-up performance approach based on transistor level simulations, in an agile development methodology. We look at how real valued modelling, using the Verilog-AMS wire that carries a real value (wreal) data type, achieves shorter simulation times in large SoCs with high frequency RF sections, low bandwidth analogue base-band sections and appreciable digital functionality including filtering and calibration blocks.
This paper discusses verification process of a mixed signal core of an HSIC PHY. After explaining the specific topic related with HSIC comparison to USB, the verification strategy is shown. The strategy is explained from the top level point of view, and detailed description is covered in subsequent sections. In following sections the system level testbench and interoperability testbenches are explained parallel to local testbenches for analog block characterization.
Don Dingee
This article suggests an innovative approach to build an optimal PMNet per application requirements, based on the definition of four standardized voltage levels (further defined as Interfaces for the Distribution of Power). Finally, it demonstrates the advantages of this approach from which regulator suppliers or designers, SoC integrators and system makers can benefit.
Based on the system specification of a typical smart meter, this article demonstrates the importance of carefully selecting the power metering IP solution so that its specification matches the standard requirements and copes with the application challenges. This article then pinpoints thoroughly the various issues that must be taken into account for the selection of the Silicon IP and helps identify the possible trade-offs between the performance of the Mixed-signal Front-end (MFE) and that of the Power and energy Computation Engine (PCE).
