Low-noise, low-power optical control loop with high-resolution ADCs, DACs, and digital control
Complete micro-ring modulator control loop PHY for wavelength stabilization, thermal tuning, and optical power control on monolithic silicon photonic platforms. The IP integrates high-resolution ADCs and DACs, digital control logic, and a customizable loop filter with configurable gain for application-specific optimization. Architected for low noise and low power operation as a foundational block in electro-photonic transceiver and WDM systems.
Process: GF Fotonix™ (45SPCLO)
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 40nm | LP | Pre-Silicon |
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MRM Control Loop PHY is a Mixed Signal Subsystem IP core from StarIC Inc listed on Semi IP Hub. It is listed with support for globalfoundries Pre-Silicon.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Mixed Signal Subsystem IP.
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