Overview
To provide the solution of MMC cards, SMIC18_MMC_01_S is integrated together by four independent IPs: SMIC18_PRG_03, SMIC18_ROSC_01, SMIC18_VDT_01 and SMIC18_POR_03. It can provide two regulated 1.8v output voltages, monitor the rising of supply voltage and detect the supply voltage. Also, an on chip ring oscillator is built in.
Learn more about Mixed Signal Subsystem IP core
VeriSilicon today announced its high-performance CPP2000 Camera Post-Processing (CPP) IP, expanding the company’s Image Signal Processing (ISP) solutions with advanced post-processing capabilities.
VeriSilicon today announced that its VC9800D Video Processing Unit (VPU) IP supports AV2 decoding, further expanding the company’s advanced video codec portfolio for next-generation video and streaming applications.
VeriSilicon’s Mature GPU, Display Processing, and DeWarp IPs Collaboratively Enable Highly Integrated, Low-Latency AR Display Processing
These enhanced IPs have successfully achieved ISO 26262 ASIL B functional safety certifications issued by TÜV NORD, an international inspection and certification institution, further validating their suitability and reliability for ADAS and autonomous driving applications.
This IP features an architecture streamlined for seamless SoC integration, delivering high-quality inference with low power consumption and a compact silicon footprint. The certificate was issued by SGS-TÜV Saar, an international testing, inspection and certification institution.
The Coral NPU is built on the open RISC-V instruction set architecture, featuring native tensor processing capabilities, supporting mainstream machine learning frameworks such as JAX, PyTorch, and TensorFlow Lite (TFLite), and utilizing open-standard tools like Multi-Level Intermediate Representation (MLIR) from the Low Level Virtual Machine (LLVM) project for compiler infrastructure.
