Vendor: SmartDV Technologies Category: HBM

HBM3 Assertion IP

HBM3 Assertion IP provides an efficient and smart way to verify the HBM3 designs quickly without a testbench.

Contact Provider Request Datasheet
Controller View all specifications

Overview

HBM3 Assertion IP provides an efficient and smart way to verify the HBM3 designs quickly without a testbench. The SmartDV's HBM3 Assertion IP is fully compliant with standard HBM3 Specification.

HBM3 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

HBM3 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Supports HBM3 memory devices from all leading vendors.
    • Supports 100% of HBM3 protocol JEDEC draft specification version 1.1.
    • Supports all the HBM3 commands as per the specs.
    • Supports programmable clock frequency of operation.
    • Support all types of timing and protocol violation detection.
    • Supports burst length of 8.
    • Supports programmable READ/WRITE Latency timings.
    • Supports Bank grouping.
    • Supports 2KB page size per channel.
    • Supports 16,32 or 48 banks per channel based on device density and channel.
    • Supports up to 16 channels per stack.
    • Supports semi-independent row and column command interfaces.
    • Supports WDQS-to-CK training.
    • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Commands rules etc.
    • All timing violations.
    • Supports all Mode registers programming.
    • Supports DBIac write and read.
    • Supports Pseudo Channel Mode Operation (32 DQ width for Pseudo Channel Mode).
    • Supports 2 Pseudo channels per channel.
    • Supports Self-Refresh Modes.
    • Supports IEEE standard 1500.
    • Supports channel density of 2 GB to 32 GB.
    • Supports 64 DQ width + Optional ECC pin support/channel.
    • Supports write data mask and data strobe features.
    • Supports for power down features.
    • Bus-accurate timing for min, max and typical values.
    • Constantly monitors HBM3 behavior during simulation.
    • Protocol checker fully compliant with HBM3 JEDEC draft specification version 1.1.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV HBM3 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure HBM3 Assertion IP functionality.

Block Diagram

HBM3 AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
HBM3 AIP
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about HBM IP core

Reducing Avoidable Memory Trips In HBM Systems

As AI and high-performance SoCs increasingly rely on HBM, memory bandwidth alone is no longer enough to maximize performance. This article discusses why the intelligent data movement and cache efficiency are critical to unlocking the full benefits of HBM-based architectures.

Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference

LLM inference is increasingly memory-bound, and HBM cost per GB now dominates system cost. Today’s HBM stacks include short on-die ECC, which tightens binning, raises price, and locks reliability policy inside the device. This paper asks a simple question: can we tolerate a much higher raw HBM bit error rate (BER) and still keep end-to-end correctness and throughput, without changing the HBM PHY or the fixed 32B transaction size?

High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the Artificial Intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like Data centers, autonomous driving systems, servers, cloud computing just to mention few domains where bandwidth and performance in a key requirement.

Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure

High-Bandwidth Memory (HBM) delivers exceptional bandwidth and energy efficiency for AI workloads, but its high cost per bit, driven in part by stringent on-die reliability requirements, poses a growing barrier to scalable deployment. This work explores a systemlevel approach to cost reduction by eliminating on-die ECC and shifting all fault management to the memory controller.

Frequently asked questions about HBM Interface IP

What is HBM3 Assertion IP?

HBM3 Assertion IP is a HBM IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this HBM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP