Vendor: Perceptia Devices Category: PLL

General Purpose All Digital Fractional-N PLL in UMC 40LP

The DeepSub™ pPLL02F is a general purpose all digital PLL featuring low-jitter and compact area suitable for many clocking applic…

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UMC 40nm LP View all specifications

Overview

The DeepSub™ pPLL02F is a general purpose all digital PLL featuring low-jitter and compact area suitable for many clocking applications at frequencies up to 2GHz. It is suitable as a clock source for moderate speed microprocessor blocks and other logic.

To give SoC designers the maximum flexibility in building complex multi-domain clock systems, pPLL02F is very small (< 0.01 sq mm) and low power (< 3.5mW). It is well suited to applications with many clock domains where each is driven by their own PLL. To simplify system design, PLL02F has an integrated power supply regulator which allows multiple instances of PLL02F to share common power supplies. Alternatively instances of pPLL02F can share supplies with the blocks that use its output clock.

pPLL02F integrates easily into any SoC design and includes all the views and models required by back end flows.

The pPLL02F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance across many processes, regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.

pPLL02F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.

Key features

  • Low jitter, suitable for many clocking applications
  • Extremely small die area (< 0.01 sq mm), using a ring oscillator
  • Output frequency can be from 1 to 400 times the input reference, up to 2GHz
  • Reference clock from 5MHz to 500MHz
  • Second-generation digital PLL architecture, providing integer and fractional multiplication
  • Primary PLL output running at the main DCO frequency for lowest noise clocking
  • Two further PLL outputs via separate postscalers
    • Post-scalers programmable from 1 to 2,040
  • Lock-detect output
  • Can generate a spread-spectrum clock from a clean reference
  • Oscillator output duty cycle better than 48 / 52%
  • Highly testable using industry standard flows
    •   ATPG vectors provided
    •   Specification of functional tests to supplement ATPG testing

Block Diagram

pPLL02F-UMC40LP block diagram

Benefits

  • Low jitter (< 18ps RMS)
  • Small size  (< 0.01 sq mm)
  • Low Power (< 3.5mW)
  • Support for multi-PLL systems
  • Easy integration
  • Fractional Multiplication

Applications

  • Moderate speed digital systems
  • Microprocessors
  • General-purpose PLL

What’s Included?

  • Datasheet
  • Detailed Verilog behavioral model
  • Timing models
  • LEF5.6 abstract for floor planning/chip assembly
  • Integration Guide
  • DFT Guide
  • Integration support
  • Characterization report
  • GDSII layout macrocell
  • CDL netlist for LVS
  • DRC, LVS and SI verification reports
  • Netlist model with accompanying documentation – allowing integration of the module in scan chains

Silicon Options

Foundry Node Process Maturity
UMC 40nm LP —

Specifications

Identity

Part Number
pPLL02F-UMC40LP
Vendor
Perceptia Devices
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Perceptia Devices
HQ: Australia
Perceptia Devices is an IP and design services provider, based in Sydney, Australia and Silicon Valley. It is focused on high-speed and ultra-low-power mixed-signal semiconductor designs. Its specialization and innovation in all-digital PLLs, a distinction from its competitors, allows it to steadily build a portfolio of proprietary and patented architectures and circuits that bring value to demanding applications. Perceptia is privately owned and self-funded.
Contact Perceptia Devices

Learn more about PLL IP core

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This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

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Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is General Purpose All Digital Fractional-N PLL in UMC 40LP?

General Purpose All Digital Fractional-N PLL in UMC 40LP is a PLL IP core from Perceptia Devices listed on Semi IP Hub. It is listed with support for umc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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