Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track ECO Generic Core Cell Library wtih LPLUS (C38).
Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track ECO Cell Library with LMINUS (C30).
Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process high performance 12-Track Metal1 Start ECO Core Cell Library.
Standard Cell (ECO) Library IP, HVT, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, HVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic process 9-Track ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track ECO_M1 Cell Library C35.
Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process high performance 12-Track Metal1 Start ECO Core Cell Library.
Specialty OSC IO IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process True 3.3V Low frequency OSC IO Cell Library.
Specialty OSC IO IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process True 3.3V Low Power Low frequency OSC IO Cell Library.
Specialty OSC IO IP, UMC 28nm HLP process
28nm Logic and Mixed-Mode HLP/RVT process True 1.8V High frequency Oscillator BOAC IO Cell Library.
Specialty OSC IO IP, UMC 0.25um Logic process
UMC 0.25um Logic process true 2.5V Oscillator IO cells.
Specialty OSC IO IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Enhancement) Logic process high frequency OSC BOAC IO.
Specialty OSC IO IP, 1MHz to 66MHz, UMC 55nm SP process
UMC 55nm SP/RVT Logic Low-K process 2.5V OD 3.3V high frequency OSC Pad.
Specialty I2C IO IP, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 1.8V/2.5V/3.3V Multi-Voltage IIC BOAC IO Cell Library.
Specialty Analog ESD IO IP, UMC 55nm CIS process
3.3V Analog ESD IO with UMC 55nm LP/HVT CMOS Image Sensor process.
Specialty Analog ESD IO IP, UMC 40nm LP process
1.8V Analog ESD IO cells with low capacitor for UMC 40nm LP process.
Specialty Analog ESD IO IP, UMC 40nm LP process
1.1V Analog ESD IO cells with low capacitor for UMC 40nm LP process.
Specialty Analog ESD IO IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, 3.3V Analog ESD IO Cell Library.
Single Port SRAM Compiler IP, UMC 90nm SP process
UMC 90nm SP/RVT Low-K Logic process high density Single Port 6T SRAM Memory Complier.
Single Port SRAM Compiler IP, UMC 90nm SP process
UMC 90nm SP/RVT/ Low-K process synchronous ultra high speed SRAM compiler.