UMC IP Cores

UMC 55nm eFlash Single-Port SRAM memory compiler

• UMC
• 55nm

55 SP Dual Port SRAM compiler with 1P4M metal option

• UMC
• 55nm

UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.

• UMC
• 65nm

UMC 90nm SPLVT ultra-high speed 1-port SRAM

• UMC
• 90nm
• SP

UMC 0.13um Al Standard performance process standard synchronous high density dual port SRAM compiler

• UMC
• 130nm
• HS

UMC 0.18UM Mixed Mode/RF; Two Port Register File

• UMC
• 180nm
• BCD

UMC 0.18UM Mixed Mode/RF; One Port Register File Memory Compiler

• UMC
• 180nm
• BCD

UMC 0.11um AL/LL Logic Process miniLib standard cell library

• UMC
• 110nm
• LL

UMC 0.11um CIS Process cell library

• UMC
• 110nm
• HS

UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony

• UMC
• 65nm
• LL

UMC 55nm LP/RVT Logic Process MPCA cell library

• UMC
• 55nm
• LP

UMC 55nm LP/LVT Logic Process MPCA cell library

• UMC
• 55nm
• LP

USB 2.0 On-The-Go PHY; UMC 28nm HLP Process

• USB 2.0
• UMC
• 28nm
• HLP

USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process cost down from FZOTG266HJ0C_A

• USB 2.0
• UMC
• 28nm
• HPC

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process

• UCIe 1.1
• UMC
• 55nm

TypeC CC channel for USBPD ; UMC 40NM LP Low-K process.

• UMC
• 40nm
• LP

Power input 3.3V, Comparator , UMC 55nm uLP/HVT Low-K Logic Process Ultra High Density (6T) C60 Core Cell Library

• UMC
• 55nm
• ULP

Power input 3.3V, Comparator ; UMC 55nm SST uLP/HVT Low-K Logic Process

• UMC
• 55nm
• ULP

2-sets voltage detector ;UMC 0.11nm Logic Mixed Mode AE Process

• UMC
• 110nm
• HS

programmable voltage detector; umc55nm eflash

• UMC
• 55nm