UMC IP Cores

UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.

• UMC
• 40nm

UMC 40nm LP with power gating & peri-HVT 1PRF

• UMC
• 40nm
• LP

UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell

• UMC
• 40nm

40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell

• UMC
• 40nm
• LP

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT

• UMC
• 40nm
• LP

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT

• UMC
• 40nm
• LP

UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating

• UMC
• 40nm

UMC 40nm LP Logic Process Ultra High Speed One-Port Register File

• UMC
• 40nm
• LP

UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell

• UMC
• 40nm

UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell

• UMC
• 55nm
• HV

UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell

• UMC
• 55nm
• HV

UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery

• UMC
• 55nm
• ULP

UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT

• UMC
• 55nm
• ULP

UMC 55nm ULP process PG-One Port Register File for periphery HVT

• UMC
• 55nm
• ULP

UMC 55nm ULP process ROM compiler with HVT peripheral

• UMC
• 55nm
• ULP

UMC 55nm ULP Low-K process One Port Register File for periphery HVT

• UMC
• 55nm
• ULP

UMC 55nm LP process with PG Dual port SRAM compiler

• UMC
• 55nm
• LP

UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.

• UMC
• 55nm

55ULP-SST 1P-RF with forward biased and UHVT periphery

• UMC
• 55nm
• ULP

55ULP-SST 1P-RF with forward biased and HVT periphery

• UMC
• 55nm
• ULP