UMC IP Cores

DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 90nm
• SP
• Silicon Proven

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• SP
• Pre-Silicon

Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 55nm
• LP
• Pre-Silicon

Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 55nm
• SP
• Pre-Silicon

DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device

• Controller + PHY + 1
• DDR2
• UMC
• 40nm
• LP
• Pre-Silicon

DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess

• Controller
• DDR2
• UMC
• 90nm
• SP
• Silicon Proven

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK …

• Controller + PHY + 1
• UMC
• 40nm
• LP
• Pre-Silicon

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS.

• Controller + PHY + 1
• UMC
• 55nm
• SP
• Pre-Silicon

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• SP
• Pre-Silicon

Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 55nm
• LP
• Pre-Silicon

Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 55nm
• SP
• Pre-Silicon

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage

• Controller + PHY + 1
• DDR2
• UMC
• 40nm
• LP
• Pre-Silicon

DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device

• Controller + PHY + 1
• DDR3
• UMC
• 40nm
• LP
• Pre-Silicon

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device

• Controller + PHY + 1
• DDR2
• UMC
• 40nm
• LP
• Pre-Silicon

DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process

• Controller
• DDR2
• UMC
• 90nm
• SP
• Pre-Silicon

DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process

• Controller + PHY + 1
• DDR2
• UMC
• 90nm
• SP
• In Production

DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 90nm
• SP
• Pre-Silicon

DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process

• Controller
• UMC
• 130nm
• HS
• Silicon Proven

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process

• Controller + PHY + 1
• DDR2
• UMC
• 130nm
• HS
• In Production

DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process

• Controller + PHY + 1
• DDR2
• UMC
• 90nm
• SP
• In Production