UMC IP Cores

UMC 90nm LL/RVT process MULTI-VOLTAGE GENERIC I/O CELL USING 3.3V GOX52 IO

• UMC
• 90nm
• LL

UMC 0.13um HS/FSG Logic Process BOAC Multi-voltage IO with Power-on Tri-state/Low Function.

• UMC
• 130nm
• HS
• Pre-Silicon

UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library

• UMC
• 28nm
• Silicon Proven

UMC 55nm uLP LowK Logic Process Ture 3.3V Generic IO Cell Library

• UMC
• 55nm
• ULP
• Silicon Proven

UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library

• UMC
• 55nm
• Silicon Proven

UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library

• UMC
• 55nm
• Pre-Silicon

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library

• UMC
• 28nm
• Silicon Proven

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library

• UMC
• 28nm
• Silicon Proven

UMC 55nm e-flash Logic Process , 3.3V Analog ESD IO cell Library

• UMC
• 55nm
• Silicon Proven

UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO

• UMC
• 90nm
• LL

UMC 90nm LL-RVT (Low-K) Process with 3.3V device analog esd IO group (with BOAC)

• UMC
• 90nm
• LL
• Pre-Silicon

UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO

• UMC
• 90nm
• LL

UMC 90nm SP/RVT process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO

• UMC
• 90nm
• SP

UMC 90nm SP/RVT Low-K process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO

• UMC
• 90nm
• SP

USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process

• USB 3.1
• UMC
• 40nm

Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.

• UMC
• 40nm
• LP
• Pre-Silicon

USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process

• USB 2.0
• UMC
• 28nm
• HPC

USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process

• UCIe 1.1
• UMC
• 55nm
• Pre-Silicon

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process

• UCIe 1.1
• UMC
• 55nm

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Enhancement) Logic Process, without internal power clamping circuit

• UCIe 1.1
• UMC
• 110nm
• HS
• Pre-Silicon