Single Port SRAM Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS Logic process synchronous, high density Single Port memory compiler.
- UMC
- 110nm
- HS
SRAM IP cores provide reusable on-chip storage structures for processors, controllers, and accelerators in modern SoC and ASIC designs.
These IP cores support fast on-chip volatile storage for caches, buffers, and tightly coupled memories, helping designers balance density, speed, power, and reliability in memory-centric subsystems
This catalog allows you to compare SRAM IP cores from leading vendors based on density, performance, power efficiency, and process node compatibility.
Whether you are designing processors, accelerators, embedded SoCs, or high-speed control systems, you can find the right SRAM IP for your application.
Single Port SRAM Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS Logic process synchronous, high density Single Port memory compiler.
Single Port SRAM Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process, 1.41um2-Bit cell Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE Logic process synchronous High-density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Enhancement) Logic process Ultra high speed Synchronous Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash HS process, Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, High density, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density synchronous Single Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 90nm SP process
UMC 90nm SP/RVT/ Low-K process synchronous Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process with row Redundancy Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 55nm eHV process
UMC 55nm eHV process, Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, Dual Port SRAM compiler with R1.
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, Dual Port SRAM compiler with LVT.
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density synchronous high density Dual Port (2RW) SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process Synchronous high density Dual Port SRAM memory compiler with input wrapper Mux.
Dual Port SRAM Compiler IP, UMC 0.11um SP process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Dual Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.11um LL process
UMC 0.11um low leakage Logic process synchronous high density Dual Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.11um eFlash/LL process
UMC 0.11um eFlash LL process Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash HS process, Dual Port SRAM compiler.