Silicon Creations Temperature/Voltage sensors are fully-integrated allowing monitoring of temperature and supply voltage levels at up to 16 points on the chip.
32Gbps SerDes IP in TSMC 12nm FFC
The relentless demand for higher data throughput in data centers and high-performance computing (HPC) systems drives the need for…
32Gbps SerDes IP in TSMC 22nm ULP
The relentless demand for higher data throughput in data centers and high-performance computing (HPC) systems drives the need for…
Low Dropout (LDO) Capless Regulator - 300 mA Output on 7nm
The ODT-LDO-IC-300M-7 is a low dropout (LDO), linear regulator for integration in a SoC.
Low Dropout (LDO) Regulator on TSMC 28nm
The ODT-LDO-28HPCT is a low dropout (LDO), linear regulator for integration in a SoC.
TSMC CLN5FF GUCIe LP Die-to-Die PHY
IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.
IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
The Wi-Fi 7 (802.11be) RF transceiver IP, operating in 2.4GHz / 5GHz / 6GHz bands, is tailored for next-generation high-performan…
Ku-Band Phased Array Tx-FE in TSMC 180nm RF
The TRV801TSM180RF IP is a Ku-Band (14GHz to 14.5GHz) Transmitter (Tx) in TSMC 180nm RF CMOS process technology.
Ku-Band Phased Array Rx-FE in TSMC 180nm RF
The TRV501TSM180RF IP is a Ku-Band (10.7GHz to 12.75GHz) Receiver (Rx) RFFE TSMC 180nm RF CMOS process technology.
General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
This Integer-N Hybrid (Digitally Aided Analog) PLL generates clock signals within broad frequency range.
USB-C 3.1/DP TX PHY for TSMC 6FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
USB 3.1 DisplayPort PHY - TSMC 10FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
LPDDR4 multiPHY V2 - TSMC28HPC+18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4X multiPHY - TSMC16FFC18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4 multiPHY V2 - TSMC16FFC18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4X multiPHY - TSMC12FFC18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4 multiPHY V2 - TSMC12FFC18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …