Quad 3.125/6.25 Gbps Backplane SerDes
TaraCom Integrated Products, Inc.
•
HQ:
USA
IP
- TSMC
- 90nm
- CIS
Compare 3,969 TSMC IP Cores from 81 vendors
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Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core
TaraCom Integrated Products, Inc.• HQ: USATRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY.
- TSMC
- 130nm
- BCD+
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100 dB of SNR, 24-bit stereo audio CODEC with headphone driver and digital mixer
Dolphin Semiconductor• HQ: FranceAmidst a rich a-la-carte offering, shCODlp-100.02 is an optimized and configuration around high performance DAC and ADC cores whi…
- TSMC
- 110nm
- In Production
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Single-carrier RF transceiver on TSMC 22nm ULL
Sequans Communications S.A.• HQ: FranceSingle-carrier RF transceiver on TSMC 22nm ULL
- TSMC
- 22nm
- ULL
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Multi-carrier RF transceiver on TSMC 22nm ULL
Sequans Communications S.A.• HQ: FranceMulti-carrier RF transceiver on TSMC 22nm ULL
- TSMC
- 22nm
- ULL
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Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
NTLab• HQ: Lithuania003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
- TSMC
- 3nm
- N3P
- Pre-Silicon
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25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
NTLab• HQ: LithuaniaFractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
- TSMC
- 3nm
- N3P
- Pre-Silicon
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Integer-N PLL, 800M-3.2G on TSMC 12nm
UniIC• HQ: ChinaThis present IP is a charge-pump Phase Locked Loop (PLL) circuit, which can cover 800MHz-3200MHz vco output frequency.
- TSMC
- 12nm
- FFC
- Silicon Proven
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PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
UniIC• HQ: ChinaThe PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.
- TSMC
- 22nm
- ULL
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DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
UniIC• HQ: ChinaThe DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.
- TSMC
- 12nm
- FFC
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DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
UniIC• HQ: ChinaThe DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM devi…
- TSMC
- 22nm
- ULL
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1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
Certus Semiconductor• HQ: United StatesA TSMC 22nm Inline, Flip Chip compatible library with GPIO, ODIO, HDMI, LVDS, & Analog Cells.
- TSMC
- 22nm
- ULL
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Specialed 20V Analog I/O in TSMC 55nm
Certus Semiconductor• HQ: United StatesA TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS This silicon-proven TSMC 55nm LP 20V ESD cell is a high-vo…
- TSMC
- 55nm
- GP
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Multi-Voltage GPIO 5V ODIO and Analog/RF I/Os in TSMC 65nm
Certus Semiconductor• HQ: United States1V/3.3V GPIO with I2C ODIO and 3.3V & 5V Analog Cells in TSMC 65nm Key attributes of this IO library include dual independent IO …
- TSMC
- 65nm
- GP
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1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm
Certus Semiconductor• HQ: United StatesHigh Performance Single-Ended / Differential I/O Macro in TSMC 16FFC This library is a production-quality, silicon-proven I/O Lib…
- TSMC
- 16nm
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Three-Speed Inline Library with Open Drain I/0 in TSMC 22nm
Certus Semiconductor• HQ: United StatesA TSMC 22nm Inline, Flip Chip compatible library with three-speed GPIOs and I2C compliant ODIO.
- TSMC
- 22nm
- ULL
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Global UniChip Corp. (GUC)• HQ: Taiwan
TSMC 3nm HBM3-8.6G PHY
- Controller + PHY + 1
- TSMC
- 3nm
- N3A
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Global UniChip Corp. (GUC)• HQ: Taiwan
TSMC 5nm HBM3-8.4G PHY
- Controller + PHY + 1
- TSMC
- 5nm
- N5
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TSMC 3nm UCIe-A 32G Die to Die Interface
Global UniChip Corp. (GUC)• HQ: TaiwanTSMC 3nm UCIe-A 32G Die to Die Interface
- TSMC
- 3nm
- N3A
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TSMC 5nm UCIe-A 32G LP Die to Die Interface
Global UniChip Corp. (GUC)• HQ: TaiwanTSMC 5nm UCIe-A 32G LP Die to Die Interface
- TSMC
- 5nm
- N5