VeriSilicon GSMC 0.18um Synchronous Programmable Low Power Via1 ROM compiler optimized for Grace Semiconductor Manufacturing Corp…
- ROM
- Pre-silicon
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
VeriSilicon GSMC 0.18um Synchronous Programmable Low Power Via1 ROM compiler optimized for Grace Semiconductor Manufacturing Corp…
VeriSilicon GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM
VeriSilicon GSMC 0.18um Synchronous Low Power Diffusion ROM compiler optimized for Grace Semiconductor Manufacturing Corporation …
GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM
Based on GSMC 0.13um 1.5V/12V eFlash process, current design of the IP detects light with photodiode.
Two Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous high density Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 65nm SP process
UMC 0.65um SP/RVT Low-K Logic process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process synchronous high density Two Port Register File SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 90nm LL process
UMC 90nm Logic process low leakage devices synchronous Low Power Single Port hihg density memory compiler.
Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm LL process
UMC 90nm LL/RVT Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy.
Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process
UMC 90nm SP/RVT Low-K Logic process Single Port SRAM (Introduce Redundancy feature to the existing FSD0A_B_SH).
Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process
UMC 90nm SP/ Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy.
One Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous Single Port SRAM.
Single Port SRAM Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process 1-port high density memory compiler.
Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process synchronous high density, Single Port SRAM compiler with the row redundancy.
Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process
UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM with redundaycy memory compiler.
Single Port SRAM Compiler IP, UMC 65nm SP process
UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM memory compiler.
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low_K Logic process synchronous high density One Port Register File compiler.
Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler with row-pair redundancy.