Vendor: Faraday Technology Category: SRAM

Dual Port SRAM Compiler IP, UMC 55nm SP process

UMC 55nm SP Low-K Logic process synchronous Dual Port RAM memory compiler.

Overview

UMC 55nm SP Low-K Logic process synchronous Dual Port RAM memory compiler.

Silicon Options

Foundry Node Process Maturity
UMC 55nm SP

Specifications

Identity

Part Number
FSF0A_A_SJ
Vendor
Faraday Technology
Type
Silicon IP

Provider

Learn more about SRAM IP core

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.

Frequently asked questions about SRAM IP cores

What is Dual Port SRAM Compiler IP, UMC 55nm SP process?

Dual Port SRAM Compiler IP, UMC 55nm SP process is a SRAM IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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