How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR2 Assertion IP
DDR2 Assertion IP provides an efficient and smart way to verify the DDR2 designs quickly without a testbench.
Overview
DDR2 Assertion IP provides an efficient and smart way to verify the DDR2 designs quickly without a testbench. The SmartDV's DDR2 Assertion IP is fully compliant with standard DDR2 Specifications and provides the following features.
DDR2 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DDR2 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Specification Compliance
- Compliant with DDR2 specifications.
- Supports all DDR2 data widths and address widths.
- Supports all DDR2 bank address widths.
- Supports all DDR2 burst lengths.
- Supports all DDR2 CAS latency.
- Supports different additive latency.
- Supports all DDR2 auto precharge for each burst.
- Supports extended mode register command.
- Supports mode register set command.
- Support for check-points include power on, Initialization and power off rules,
- Support for state based rules, Active Command rules,
- Support for Read/Write Command rules etc.
- Support for all timing violations.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV DDR2 VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure DDR2 Assertion IP functionality.
Block Diagram
DDR2 AIP block diagram
Benefits
- Runs in every major formal and simulation environment.
What’s Included?
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
DDR2 AIP
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
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Frequently asked questions about DDR Interface IP
What is DDR2 Assertion IP?
DDR2 Assertion IP is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.