TPU IoT/Edge Licensable Hardware IP
The Prodigy is the first Universal Processor combining General Purpose Processors, High Performance Computng (HPC), Artficial Int…
- NPU
AI and Machine Learning accelerator IP cores are specialized hardware blocks designed to accelerate neural network inference and machine learning workloads in modern SoC and ASIC designs.
These IP cores, often referred to as NPU (Neural Processing Units) or AI accelerators, deliver high performance and energy efficiency for applications such as computer vision, speech recognition, natural language processing, and autonomous systems.
This catalog allows you to compare AI/ML accelerator IP cores from leading vendors by performance (TOPS), power efficiency, supported frameworks, and process node compatibility.
Whether you are targeting edge AI devices, automotive systems, consumer electronics, or data center acceleration, you can identify the most suitable AI IP for your design.
TPU IoT/Edge Licensable Hardware IP
The Prodigy is the first Universal Processor combining General Purpose Processors, High Performance Computng (HPC), Artficial Int…
Neural Network Acceleration for Automotive AI
State-of-the-art NPU for automotive inference, with many features built-in to maximize performance for a wide range of automotive AI applications.
So_ip_edte_un_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consistin…
Area-efficient decision tree ensemble evaluation core based on serial evaluation of ensemble members
So_ip_edte_un_s core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consistin…
Decision tree ensemble evaluation core based on parallel evaluation of ensemble members
So_ip_edte_smpl_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consist…
Decision tree ensemble evaluation core based on serial evaluation of ensemble members
So_ip_edte_smpl_s core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consist…
Decision tree ensemble classifier inference core
So_ip_idte core can be used create an ensemble of decision trees directly in hardware.
Decision tree evaluation core using serial architecture
So_ip_edt_un core can be used to implement the decision tree with the previously defined structure directly in hardware.
Decision tree evaluation core using pipelined architecture
So_ip_edt_smpl core can be used to implement the decision tree with the previously defined structure directly in hardware.
Configurable transformer accelerator
For fast, low-power edge AI inference on Stories260K, Stories15M, SmolLM 135M, LLaMA 3.2, and custom models, supporting FP32, INT8, and INT4.
VisionNet v1.0 is a configurable CNN accelerator IP designed to deliver efficient edge inference for vision workloads.
For sophisticated workloads, DeepTransformCore is optimized for language and vision applications.
Revolutionary dataflow architecture optimized for AI workloads with spatial compute arrays, intelligent memory hierarchies, and r…
The Neural-Network Accelerators (NACC) improves the inference performance of neural networks.
Safety Enhanced GPNPU Processor IP
Automotive applications are uniquely demanding for any AI acceleration solution.
AI DSA Processor - 9-Stage Pipeline, Dual-issue
NI900 is a DSA processor based on 900 Series.
Unified Architecture for Cutting-Edge Intelligence
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…