RC Oscillator IP, Output: 12KHz, UMC 65nm SP process
Internal-RC, trimmable fixed frequency 12KHz.
- UMC
- 65nm
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
RC Oscillator IP, Output: 12KHz, UMC 65nm SP process
Internal-RC, trimmable fixed frequency 12KHz.
RC Oscillator IP, Output: 50MHz, UMC 0.18um G2 process
Internal-RC, frequency 50MHz.
RC Oscillator IP, Output: 25MHz / 33MHz, UMC 0.18um eFlash/G2 process
UMC 0.18um eFlash process, Internal-RC, trimmable frequency selected 25MHz/33MHz, VCCA=1.2V~1.8V, VBG=0.615.
RC Oscillator IP, Output: 20MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency 20MHz, VCCA=1.6V~2.0V VBG=0.615V, UMC 0.18um GII Logic process.
RC Oscillator IP, Output: 50MHz / 70MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency selected 50MHz/70MHz.
RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz.
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process.
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller u…
UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller…
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Enhance…
Band Gap IP, Input: 1.08V - 1.32V, VBG=0.6V, UMC 90nm LL process
Input 1.08V-1.32V, VBG=0.6V, Band Gap, LL process, UMC 90 nm LL Logic/RVT Low-K process.
Band Gap IP, Input: 0.9V - 1.1V, VBG=0.5V, UMC 90nm SP process
Input 0.9V-1.1V, VBG=0.5V, Band Gap, UMC 90nm SP/RVT Logic Low-K process.
Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 90nm SP process
Input 2.25V-2.75V, VBG=1.23V, Bnad Gap, SP process, UMC 90nm SP/RVT (FSG) Logic process.
Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 65nm SP process
Input 2.25V-2.75V, VBG=1.23V, Band Gap, SP process, UMC 65nm SP/RVT Low-K Logic process.
Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 55nm SP process
Input 2.25V-2.75V, VBG=1.23V, Band Gap, SP process, UMC 55nm SP/RVT Low-K Logic process.
Band Gap IP, Input: 2.0V - 4.0V, VBG=1.23V, UMC 0.18um G2 process
Input power range = 2.0V-4.0V, VBG=1.23V, bandgap, UMC 0.18um GII Logic process.
Band Gap IP, Input: 1V - 1.5V, VBG=0.8V, UMC 0.11um HS/AE process
Input 1V-1.5V, VBG=0.8V bandgap, UMC 0.11um HS/AE (AL Enhancement) Logic process.