Audio ADDA IP, 24 bits / 96KHz, UMC 0.11um HS/AE process
24-Bit 96KHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver, UMC 0.11um HS/AE (AL Enhancement) Logic process.
- UMC
- 110nm
- HS
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Audio ADDA IP, 24 bits / 96KHz, UMC 0.11um HS/AE process
24-Bit 96KHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Audio ADDA IP, 24 bits / 96KHz, UMC 0.11um HS/AE process
24-Bit 96KHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver, UMC 0.11um HS/AE Logic process.
A/D Converter IP, 11 bits, 1Msps, UMC 90nm LL process
It is a 11-Bit 1MSPS SAR Analog-to-Digital converter, UMC 90nm LL/RVT Low-K process.
A/D Converter IP, 10 bits, 1Msps (Max clock rate: 13MHz), with 8-to-1 input MUX, UMC 90nm SP process
FXAnalog-to-Digital converter143HD0A with 8-to1 Mux for FTC, UMC 90um SP/RVT Low-K Logic process.
A/D Converter IP, 11 bits, 1Msps (Max clock rate: 13MHz), with 8-to-1 input MUX, UMC 90nm SP process
SAR Analog-to-Digital converter with 8-to-1 Mux and resistor-type touch panel deriver, UMC 90nm SP/RVT Low-K process.
A/D Converter IP, 10 bits, 40MHz, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process, 1.2V/Bi-channels 40MHz 10-Bit Pipelined Analog-to-Digital converter.
A/D Converter IP, 10 bits, 1Msps, UMC 65nm LL process
1MSPS 10-Bit SAR Analog-to-Digital converter, UMC 65nm LL/RVT Low-K Logic process.
A/D Converter IP, 12 bits, 80Msps, I-Q Channels, UMC 55nm SP process
12-Bit 80MSPS Dual-channel Pipelined Analog-to-Digital converter, UMC 55nm SP/RVT Low-K Logic process.
A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 55nm SP process
10-Bit 1MSPS SAR Analog-to-Digital converter with 8-to-1 Mux (all C-type), UMC 55nm SP/RVT Low-K Logic process.
A/D Converter IP, 10 bits, 80Msps, UMC 0.18um Logic/Mixed-Mode process
10-Bit 80MSPS Differential Analog-to-Digital converter, UMC 0.18um Logic/Mixed-Mode process.
A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.18um G2 process
10-Bit 1MSPS single-end Analog-to-Digital converter with 8-to1 Mux, UMC 0.18um GII Logic process.
A/D Converter IP, 10 bits, 40Msps, UMC 0.18um Logic/Mixed-Mode process
10-Bit 40MSPS 2-channel Differential Analog-to-Digital converter, UMC 0.18um Logic/Mixed-Mode process.
A/D Converter IP, 10 bits, 1Msps, UMC 0.13um LL/FSG process
UMC 0.13um LL/FSG process, 1MSPS 10-Bit SAR Analog-to-Digital converter with rail-to-rail input feature.
A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.13um LL/FSG process
FXAnalog-to-Digital converter140HC0L with 8-to1 Mux, UMC 0.13um LL/FSG Logic process.
A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.13um LL/FSG process
10-Bit 1MSPS SAR Analog-to-Digital converter with 8-to-1 Mux, UMC 0.13um LL/FSG Logic process.
A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, SAR type, UMC 0.11um HS/AE process
10-Bit 1MSPS SAR Analog-to-Digital converter with 8-to-1 Mux (All C-type), UMC 0.11um HS/AE (AL Enhancement) Logic process.
A/D Converter IP, 12 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/AE process
12-Bit 1MSPS SAR Analog-to-Digital converter with 8-to-1 Mux (All C-type), UMC 0.11um HS/AE (AL Enhnacement) Logic process.
A/D Converter IP, 12 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/AE process
12-Bit 1MSPS SAR Analog-to-Digital converter with 8-to-1 Mux, UMC 0.11um HS/AE (AL Enhancement) Logic process.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a Voltage Detector (VDT) circuit for power management application.