Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,…
- UMC
- 28nm
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,…
Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of…
Input 50M-210MHz, output 50M-210MHz.
Input 10M-70MHz, output 10M-70MHz.
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 2…
Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process.
Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process.
Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process.
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,…
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,…
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,…
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 2…
An ADDLL operate at 50MHz~210MHz.
IP
IP
SMIC 0.13um Power Management Kit,1.2v operating voltage
SMIC 0.13um Power Management Kit Library
SMIC 0.11um Power Management Kit,1.2v operating voltage
SMIC 0.11um Power Management Kit Library
SMIC 90nm Power Management Kit, 1.2v operating voltage
SMIC 90nm Power Management Kit Library
LDO External NPN Device Series (Vin=1.62-3.6V; Vo=1.05-1.15V; Io=1A)
LDO: The SGC79100 is a low-dropout, high current, fast response, low quiescent linear regulator IP solution with external NPN (or…
DC-DC Boost Optimal Response High Power Series (Vin=2.3-5.5V; Vo=4.5-9.5V; IL=3A)
DC-DC PWM BOOST: The DCDC SGC68 is an optimal response, high output current, step up switched DC-DC regulator IP.
DC-DC Buck Ultra Fast Response High Power Series (Vin=1.6-1.98V; Vo=0.725-1.325V; IL=6A)
DC-DC PWM BUCK: The DCDC SGC67 is an ultra fast response, high output current, step down switched DC-DC regulator IP.