Ultra low Power High Speed 600MHz lnteger-N PLL IP Core
An ultra-low-power programmable fractional-N at 600MHz, phase-locked loop (PLL) for frequency synthesis available at 22nm.
- PLL
- In Production
- Immediate
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Ultra low Power High Speed 600MHz lnteger-N PLL IP Core
An ultra-low-power programmable fractional-N at 600MHz, phase-locked loop (PLL) for frequency synthesis available at 22nm.
Ultra low Power High Speed 800MHz Frac-N PLL IP Core
A programmable on-the-fly Fractional-N PLL at 800MHz is required to lock to an incoming clock source and produce an output clock …
Low Power High Speed 1GHz Frac-N PLL IP Core
An ultra-low-power programmable fractional-N at 1GHz phase-locked loop (PLL) for frequency synthesis available at 28nm.
Low Power High Speed 1.2GHz Frac-N PLL IP Core
A programmable on-the-fly Fractional-N PLL at 1.2GHz is required to lock to an incoming clock source and produce an output clock …
Ultra low Power 1.4GHz Frac-N PLL IP Core
An ultra-low-power programmable fractional-N (ULF), phase-locked loop (PLL) at 1.4GHz for frequency synthesis available at 40nm.
Low PowerHigh Speed 1.6GHz Frac-N PLL IP Core
A programmable on-the-fly Fractional-N PLL at 1.6GHz is required to lock to an incoming clock source and produce an output clock …
High Speed 1.5GHz Frac-N PLL IP Core
A programmable on-the-fly Fractional-N PLL at 1.5GHz is required to lock to an incoming clock source and produce an output clock …
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>10b ENOB,
>80 dB SNR over 50 Hz bandwidth.