UMC L130SP 130nm Clock Generator PLL - 118MHz-590MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- UMC
- 130nm
- SP
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
UMC L130SP 130nm Clock Generator PLL - 118MHz-590MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L180G 180nm Clock Generator PLL - 50MHz-250MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L150HS 150nm Clock Generator PLL - 140MHz-700MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L150HS 150nm Clock Generator PLL - 70MHz-350MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L180G 180nm Clock Generator PLL - 100MHz-500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L130SP 130nm Clock Generator PLL - 59MHz-295MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL018G 180nm Clock Generator PLL - 110MHz-550MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL013G 130nm Clock Generator PLL - 136MHz-680MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL018G 180nm Clock Generator PLL - 55MHz-275MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL015LV 150nm Clock Generator PLL - 140MHz-700MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL018E 180nm Clock Generator PLL - 65MHz-325MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL015G 150nm Clock Generator PLL - 130MHz-650MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL015G 150nm Clock Generator PLL - 65MHz-325MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL018E 180nm Clock Generator PLL - 130MHz-650MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL015LV 150nm Clock Generator PLL - 70MHz-350MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL013G 130nm Clock Generator PLL - 68MHz-340MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL013LV 130nm Clock Generator PLL - 320MHz-1600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL013LV 130nm Clock Generator PLL - 80MHz-400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L130HS 130nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L150HS 150nm Deskew PLL - 70MHz-350MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.