1.0~3.6V input, loading 20mA, 0.9V output with VBG=0.75V Linear Regulator, UMC 55nm ULP/UHVT Low-K Logic Process
- UMC
- 55nm
- ULP
Power management IP cores are essential components in modern SoC and ASIC designs, enabling efficient power regulation, distribution, and energy optimization.
These IP cores include functions such as voltage regulators, DC-DC converters, LDOs, battery management, and power monitoring, ensuring reliable and energy-efficient system operation.
This catalog allows you to compare power management IP cores from leading vendors based on efficiency, power consumption, integration level, and process node compatibility.
Whether you are designing mobile devices, automotive systems, IoT products, or high-performance computing platforms, you can find the right power management IP for your system.
1.0~3.6V input, loading 20mA, 0.9V output with VBG=0.75V Linear Regulator, UMC 55nm ULP/UHVT Low-K Logic Process
Input 1.0V-3.6V, VBG=0.75V, Band Gap, UMC 55nm ULP Low-K Logic process
Power on Reset IP, Input: 3.3V, Vrr=2.81V, Vfr=2.81V, UMC 55nm SP process
Vrr=2.81V Vfr=2.81V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset,special request, UMC 55nm SP/RVT LowK Logic Process
Power on Reset IP, UMC 0.25um MS process
Vrr=1.6V Vfr=1.4V, core type, Power On Reset with tunable reset time by external capacitor, UMC 0.25um Logic/MMC process.
Power on Reset IP, UMC 0.25um process
Power on Reset with Vrr and Vfr., Power On Reset, UMC 0.25um Logic process.
Power on Reset IP, UMC 0.25um process
Power on Reset with Vrr and Vfr., Power On Reset, UMC 0.25um Logic process.
Power on Reset IP, UMC 0.25um process
Power on reset using 0.25um process, A-type IO, Urr=1.8V, Ufr=1.6V, UMC 0.25um Logic process.
Power on Reset IP, UMC 0.11um eFlash process
Power on reset(POR) block, UMC 0.11um e-flash process.
Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process
Vrr=2.2V Vfr=2.0V, B type IO, input VCCK=1.2V VCC3IO=3.3V, 3.3V Power On Reset, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Power on Reset IP, Input: 3.3V, UMC 0.11um eFlash process
Vrr=2.2V, Vfr=2.0V, A type IO, 3.3V Power On Reset, UMC 0.11um AL eFlash process.
Power on Reset IP, Input: 2.5V, UMC 0.25um MS process
Power on Reset circuit tolerant with 0.25um, 2.5V MMC and Logic process VCC=2.5V, B type IO, Power On Reset, UMC 0.25um Logic pro…
Power on Reset IP, Input: 2.5V, UMC 0.25um process
Vrr=1.8V Vfr=1.6V, VCC=2.5V, Ivcc=13.4uA, B type IO, Power On Reset, UMC 0.25um Logic process.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA, Core type, Power On Reset, UMC 0.18um GII Logic process.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA, D type IO, Power On Reset, UMC 0.18um GII Logic process.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA, C type IO, Power On Reset, UMC 0.18um GII Logic process.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA, B type IO, Power On Reset, UMC 0.18um GII Logic process.
Power on Reset IP, Input: 1.2V, Vrr=0.8V, Vfr=0.65V, UMC 55nm LP process
Vrr=0.8V, Vfr=0.65V, input VCC=1.2V, 1.2V Power On Reset, UMC 55nm 2T LP/RVT Low-K Logic process.
Power on Reset IP, Input: 1.2V, Vrr=Vfr=0.8V, UMC 55nm LP process
Vrr=Vfr=0.8V, input VCC=1.2V, 1.2V Power On Reset, UMC 55nm 2T LP/RVT Low-K Logic process.
Power on Reset IP, Input: 1.2V, UMC 0.13um LL/FSG process
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=10.7uA, Core type, Power On Reset, UMC 0.13um LL Logic(FSG) process.
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA, HS process with B-type IO., Power On Reset, UMC 0.13um HS/FSG Logic process.