Power on Reset IP, Input: 1.8V, UMC 0.153um MS process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit), Power On Reset, UMC 0.153um Mixed-Mode/Logic process.
- Power On Reset (POR)
Power management IP cores are essential components in modern SoC and ASIC designs, enabling efficient power regulation, distribution, and energy optimization.
These IP cores include functions such as voltage regulators, DC-DC converters, LDOs, battery management, and power monitoring, ensuring reliable and energy-efficient system operation.
This catalog allows you to compare power management IP cores from leading vendors based on efficiency, power consumption, integration level, and process node compatibility.
Whether you are designing mobile devices, automotive systems, IoT products, or high-performance computing platforms, you can find the right power management IP for your system.
Power on Reset IP, Input: 1.8V, UMC 0.153um MS process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit), Power On Reset, UMC 0.153um Mixed-Mode/Logic process.
Linear Regulator IP, Output: 1.8V/150mA, UMC 0.162um Logic process
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.162um Logic process.
Linear Regulator IP, Output: 1.8V/150mA, UMC 0.153um MS process
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.153um Mixed-Mode/Logic process.
Linear Regulator IP, Output: 4.2V/1000mA, UMC 0.153um MS process
5.0V to 4.2V Linear Regulator with 1000mA driving capability, UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode process.
DC-DC IP, Input: 3.3V, Output: 3.3V/300mA, UMC 0.153um MS process
5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator, UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode proces…
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.153um MS process
Pulse Width Modulation, boosting voltage from 3.3V to 5V/50mA driving capability, Ivcca=140uA@Idrive=0, UMC 0.153um Logic/Mixed-M…
Power on Reset IP, Input: 1.8V, UMC 0.162um Logic process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit), Power On Reset, UMC 0.162um Logic process.
Band Gap IP, Input: 2.0V - 3.6V, VBG=1.22V, UMC 0.153um MS process
Input 2.0V-3.6V, VBG=1.22V, Band Gap, UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode process.
Real-Time-Clock Analog, Include 32K XOSC, Capaless LDO, POR, VDT - HHGrace 110nm
Real-Time-Clock Analog, Include 32K XOSC, Capaless LDO, POR, VDT - HHGrace 110nm
Power On Reset, Detector 3.3V and 1.8V Domain - UNT 180nm
Power On Reset, Detector 3.3V and 1.8V Domain - UNT 180nm
IP