Vendor: NTLab Category: EEPROM

512bit EEPROM IP with configuration 16p2w16bit

180SMIC_EEPROM_09 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits which is org…

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SMIC 180nm G Pre-Silicon View all specifications

Overview

180SMIC_EEPROM_09 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits which is organized as 16 pages of 2 words by 16 bit with single-bit output data and parallel write data. Data writing in EEPROM consists of 2 phases - erasing and programming. Data to be written in EEPROM are applied to din1<15:0>, din0<15:0> inputs. Erasing words of a page is performed by setting to “1” the signal hv_on, with the signal erase is at state “1”. Data din1<15:0>, din0<15:0>, page address adr_p<3:0> and word address in page adr_w must not be changed throughout the whole cycle of erasing (i.e. while hv_on = “1”). Words are programmed when the signal hv_on= “1” and the signal PROG= “1”. Data reading is performed using the sample signal. Memory is optimized for usage in the industrial and commercial applications, requiring low power consumption and supply voltage.

Key features

  • SMIC EEPROM CMOS 0.18 um
  • High density of memory cells
  • Programming and erasing data by one high-voltage pulse
  • Programming and erase time – 2 ms (determined by specification of the SMIC EEPROM cell)
  • Page writes allowed
  • Data retention over 10 years (endurance 105 cycles, determined by SMIC technology)
  • Low power dissipation in standby and active mode
  • Internally organized 16(bit per word) x 2(word per page) x 16(page) bit

Block Diagram

180SMIC_EEPROM_09 block diagram

Applications

  • Access control systems
  • Radio-frequency identification systems, smart cards
  • Electronic devices with battery power
  • Chip serial ID and chip safety
  • Electronic tags UHF band

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Silicon Options

Foundry Node Process Maturity
SMIC 180nm G Pre-Silicon

Specifications

Identity

Part Number
180SMIC_EEPROM_09
Vendor
NTLab
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

NTLab
HQ: Lithuania
Contact NTLab

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Frequently asked questions about EEPROM IP cores

What is 512bit EEPROM IP with configuration 16p2w16bit?

512bit EEPROM IP with configuration 16p2w16bit is a EEPROM IP core from NTLab listed on Semi IP Hub. It is listed with support for smic Pre-Silicon.

How should engineers evaluate this EEPROM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this EEPROM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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