The synthesizer forms clock signal with frequency from 50 to 800 MHz.
The synthesizer forms clock signal with frequency from 50 to 800 MHz. It consists of the ring VCO with frequency from 400 to 800 MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter and programmable clock divider to obtain a required output frequency. Output frequency is calculated by formula: FLO = (Fref*N)/(R*C). Power supply is 1.2V. Output signal is CMOS compatible.
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 65nm | GP | Silicon Proven |
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50 - 800 MHz phase-locked loop is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
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