The CMOS high-frequency divider consists of two independent circuits.
The CMOS high-frequency divider consists of two independent circuits. The first divider is a set of serially connected CMOS dividers with a dividing ratio 2. The second circuit is based on ECL logic and has differential signal. The reference current source of ECL circuit has temperature dependent and temperature independent modes. The buffer-commutators are used to output the signal of a frequency divided by 2, 64 or 128.
The block is fabricated on TCMS BiCMOS 0.18 um technology.
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | BCDG2 | Silicon Proven |
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2/64/128 CMOS/ECL PLL high-frequency divider is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
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