VLSI Plus Announces Multiplexing CSI2 Transceiver IP core

Raanana, Israel, December 11, 2014: VLSI Plus, a leading provider of MIPI^® CSI2 compliant IP cores, today announced the availability of the CSI2-MUX-A1-F – a MIPI® CSI2 transceiver, connecting to up to 4 CSI2 camera inputs, and outputting a multiplexed CSI2 stream with 4 data lanes, at up to 1.5Gbps per lane.

This product comprises modified versions of proven VLSI Plus’ IP cores, with dedicated glue logic and control. Each camera input is connected to a modified VLSI Plus SVR-CS4-F serial video receiver, which converts the serial inputs to parallel stream. The parallel streams are then assigned 4 CSI2 virtual channels, and asserted at the parallel input ports of a modified VLSI Plus’ SVT-CS4-AP2 multiplexing serial video transmitter

VLSI Plus (www.vlsiplus.com) is a boutique IP house, specializing in digital video and, in particular, in IP cores complying with MIPI® CSI2 Camera Serial Interface standard. VLSI Plus is the first CSI2 IP core vendor to get MIPI® IOL certificate.

Yoav Lavi, founder and CEO of VLSI Plus said: “The availability of high performance low cost CSI2 cameras on one hand, and high performance application processors on the other hand, opens a wide range of system opportunities for low cost systems where images from several cameras are congregated. Applications include generation of a stereo image, multiple-input super-resolution techniques, extended depth-of-field images, extended dynamic range images, and many others.”

Lavi added: “this IP core is a first in a series. The FPGA version will be followed by an ASIC version; then forthcoming CSI2 versions with more lanes and higher data rates will be added, as well as geometrical multiplexing where more than 4 inputs are to be supported”.