10-bit 1-channel 100 MSPS ADC

The 10-bit 100 MSPS ADC employs a high-performance front-end sample-and-hold with differential multi-stage pipelined architecture and output error correction logic. The biasing circuit and the clock generator are also included to provide a complete ADC. The ADC operates with sampling rate up to 100 MSPS and a corresponding input clock up to 200 MHz (input clock is divided by two). The ADC can be configured to achieve addition power saving at low sampling rate, supports standby mode and features the excellent dynamic and static performance, wide bandwidth inputs, low power consumption and compact die area.
The block is designed on TSMC CMOS 65 nm technology.

• TSMC CMOS 65 nm
• Resolution 10-bit
• 1 channel
• Different power supplies for digital (1.2 V) and analog parts (1.2 V)
• Sampling rate up to 100 MSPS
• Standby mode (current consumption <10 µA)
• Low-power dissipation:
  • 34 mW at 100 MSPS
  • 21 mW at 50 MSPS
• Differential full-scale input range peak-to-peak 1 V
• Dynamic performance
  • 66.0 dB SFDR, 54.2 dB SINAD at 50 MSPS and fin = 10.7 MHz
  • 66.3 dB SFDR, 53.0 dB SINAD at 100 MSPS and fin = 10.7 MHz
• Differential Non-Linearity 0.79 LSB
• Integral Non-Linearity 0.94 LSB
• Compact die area 0.26 mm2

• WiFi, WiMax
• Mobile Communications
• High quality imaging video systems
• Data acquisition systems
• Portable ultrasound and digital beam-forming systems

• Schematic or NetList
• Abstract model (.lef and .lib files)
• Layout view (optional)
• Behavioral model (Verilog)
• Extracted view (optional)
• GDSII
• DRC, LVS, antenna report
• Test bench with saved configurations (optional)
• Documentation