A New Generation of LPDDR
June 15, 2020
Ever-increasing expectations for mobile device performance have been driving the need for versatile mobile memory solutions. JEDEC has recently announced the publication of JESD209-5A which is equipped to match the latest bandwidth, power, performance, and reliability trends. The JESD209-5A standard offers several feature enhancements in addition to the existing LPDDR5 standard, including support for Partial Array Refresh Control (PARC), Refresh Management, Enhanced Write Clock (WCK) Always On Mode, Optimized Refresh, etc. This blog will briefly discuss the new features introduced in the updated LPDDR5 standard which has helped to significantly reduce power consumption and improved in data integrity.
To read the full article, click here
Related Semiconductor IP
- LPDDR5T / LPDDR5X / LPDDR5 Controller
- LPDDR5 Controller - Validates memory controllers for high-speed, power-efficient performance
- LPDDR5 IP solution
- Simulation VIP for LPDDR5
- LPDDR5 Synthesizable Transactor
Related Blogs
- SiFive; Empowering A New Era of Data Center Innovation
- Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring
- LPDDR6: A New Standard and Memory Choice for AI Data Center Applications
- Charting a Productive New Course for AI in Chip Design
Latest Blogs
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Efficiency Defines The Future Of Data Movement
- Why Standard-Cell Architecture Matters for Adaptable ASIC Designs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production