D2D PHY IP Listing

High-performance, low-latency PHY for D2D connectivity The UltraLink™ Die-to-Die (D2D) PHY enables SoC providers to deliver more …

• GlobalFoundries
• 12nm
• LP
• Silicon Proven

The UCIe PHY & D2D Adapter IP portfolio includes 32Gbps UCIe- (UCIe-A) & Standard (UCIe-S) cores as per the latest UCIe v1.1 spec…

• UCIe

IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.

• TSMC
• 5nm
• N5FF

Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…

• Verification IP

Streamline Ventana technology integration into high-performance systems, fully leveraging third-party IP, while applying RISC-V s…

• CPU

A UCIe solution ready to support any protocol layer The D2D Adapter for UCIe combined with the UCIe PHY from a UCIe solution read…

• UCIe

The Die-to-Die Controller IP, optimized for latency, bandwidth, power, and area, enables efficient inter-die connectivity in serv…

• Custom

The second-generation high-performance RISC-V CPU delivers a major leap in compute capability, designed for deployment across dat…

• CPU

Industry , AXI5-Stream Solution for UCIe D2D Stacks The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Strea…

• UCIe

Industry , Silicon Proven, 32 Gbps per pin, backed by a portfolio of verification tools, PHY interoperability and integration.

• UCIe

The Racyics UCIe PHY is an energy-efficient chiplet interconnect IP solution for consumer and automotive applications.

• GlobalFoundries
• 22nm
• FDX

Our mass production-proven IPTD2D-A D2D Interconnect IP Solutions offer industry- power efficiency, performance, and low latency,…

• Custom

BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP.

• Custom

The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and…

• Custom

Scalable RISC-V CPUs for Data Center, Automotive, and Intelligent Edge

• CPU

The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package.

• UCIe

The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package.

• UCIe

The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heter…

• UCIe

The ODT-UCIE-UNI-TX-16GXX-16FFCT is a low power D2D transmitter IP in TSMC 16FFC process.

• TSMC
• 16nm
• FFC

The ODT- UCIE-UNI-RX-16GXX-S8 is a low power D2D receiver IP in Samsung 8nm process.

• Samsung
• 8nm