MSquare's PCI Express 4.0 PHY IP includes a high-speed, -efficient, and cost-effective transceiver to turbocharge today's high-pe…
- Single-Protocol PHY
MSquare's PCI Express 4.0 PHY IP includes a high-speed, -efficient, and cost-effective transceiver to turbocharge today's high-pe…
Full compatible with PIPE4.2 interface specification
This 1-lane to 4-lane PCIE PHY includes all high-speed analog functions for high-speed data transport between chips over PCBs and…
PCIe PHY and controller solution
Brite 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance.
The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for hi…
IP
IP
IP for Automotive Applications
M31 provides the variety IP types which meet ISO 26262 vehicle function safety requirements for the different applications in the…
PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 40LP
PCIe Gen 3.1 transmission is supported by (PCIe 3.1) x4 PHY IP.
PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
(PCIe 3.1) x4 PHY IP supports PCIe3.1 transmission.
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 5.0 Base Specification with support of PIPE 5…
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 40LP
Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard.
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
The Peripheral Component Interconnect Express Gen3 PHY IP with PIPE 4.3 interface standard supported by this that complies with P…
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface sta…
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface sta…
Gen-Z Physical Layer for PCIe IP Core
The IntelliProp IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe is an IP Core that allows companies to attach a Gen-Z core to a PCIe …
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
This Peripheral Component Interconnect Express Gen3 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 in…
Spartan-3 LogiCORE Endpoint PIPE for PCI Express (PCIe)
Version 1.8 Now Supports Spartan™-3/3E/3A The Xilinx Spartan-3 LogiCORE™ Endpoint PIPE for PCI Express® (PCIe®) protocol layer co…
Our SerDes architecture is in production in processes ranging from 12nm to 180nm and at rates from 100Mbps to 32.75Gbps and prove…
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.13um HS/FSG process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with Low Power feature, UMC 0.13um HS/FSG Logic process.