The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
- PCIe Gen4
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
LEE Flash ZT (ZT) achieves automotive grade temperature and quality grade.
sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler r…
Low frequency XTAL oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of clocks.
Low frequency 32-kHz RC oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of voltage regulators and clocks.
USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm)
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK(Built-in Cl…
USB 1.1 PHY in TSMC(40nm, 55nm, 90nm ULP process )
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
ASIC IP-core for very-high-throughput decoding (>20G) of 3GPP 5G Release 15
Very high throughput (>20 Gbps) LDPC decoder and encoder for 3GPP 5G Release 15.
PowerVR Series9XM Graphic Processor
The PowerVR Series9XM family features include: an scalable compute cluster architecture; high efficiency compression technology i…
PowerVR Series9XE Graphic Processor
The PowerVR Series9XE family features include: an scalable compute cluster architecture; high efficiency compression technology i…
AHB Single Channel DMA Controller
The DMA is a configurable single channel direct memory access controller.
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction.
IP
IP
USB2.0 PHY - SMIC 110nm generic
IP
12 Bit ADC - SMIC 110nm generic
IP
IP
Power regulator - SMIC 110nm generic
IP
Power regulator - SMIC 110nm generic
IP
IP