The BLE5T55ULP RF IP is designed for TSMC 55nm ULP Process.
- TSMC
- 55nm
- GP
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The BLE5T55ULP RF IP is designed for TSMC 55nm ULP Process.
Bluetooth 5.0 LE and Sub-GHz Transceiver
The BLE5SUBGT40ULP RF IP is designed for TSMC 40nm ULP Process.
SATA Bridge Platform (Optional: AES, Hardware Datapath)
The IntelliProp SATA Bridge Platform is an extensible IP Core which encompasses a SATA Device core, a SATA Host core, along with …
The IntelliProp SATA Host AHCI (IPC-SA156A-HI) is an industry standard Serial-ATA (SATA) host interface core that enables custome…
The IntelliProp IPC-NV164A-HI NVMe Host Accelerator IP Core provides a simplified, high-bandwidth interface to industry standard …
The LVDS transceiver IP is a SERDES pair that clearly interprets 12–bit parallel bus into serial stream.
Special I/O-eMMC/SDIO in TSMC(22nm, 28nm, and 40nm)
SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwid…
Standard Cell Library in TSMC (12nm~180nm)
M31 provides a variety of cell libraries, including Ultra-High Density Standard Cell Library (HDSC), General Purpose Standard Cel…
General Purpose I/O (GPIO) in TSMC(12nm,16nm,22nm, 28nm, 40nm, 90nm BCD+, 152nm BCD, 180nm BCD)
GPIO is a general-purpose input/output unit that provides basic input/output functionalities.
Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
M31 memory compilers are designed with high industrial standard which provides the memory solutions for density, power, and perfo…
PCIe 4.0 PHY in TSMC(6nm,7nm, 12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
ONFI I/O 6.0/5.1/5.0 IP in TSMC(3nm, 5nm, 6nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm)
ONFI I/O is a non-volatile memory interface technology with high bandwidth capabilities, mainly developed for flash storage appli…
32-channel 64-QAM/256-QAM J.83 Annex B Cable Modulator
The IPrium-J83B-C-Modulator IP Core is 32-channel J.83B Modualtor with MAX5861 (MAX5862) support.
The RF libraries include analog signal pads and ESD protection components for RF applications.
The ONFI library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage referen…
2.5V 5V Tolerant GPIO Inline IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant.
2.5V 5V Tolerant GPIO Staggered IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant.
The LVDS I/O is a three-module design (input, output and reference block).
The LVDS I/O is a three-module design (input, output and reference block).
The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring…