Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
M31 memory compilers are designed with high industrial standard which provides the memory solutions for density, power, and perfo…
Overview
M31 memory compilers are designed with high industrial standard which provides the memory solutions for density, power, and performance optimization. M31 memory compilers are using industry leading techniques to help customers to achieve their various SOC projects.
Meanwhile, M31 Memory Compiler IP was certified with ASIL D of ISO 26262 on April, 2019.
Key features
- Synchronous read/write operation
- Low leakage current and lower operation power consumption
- Minimum metal layer requirement: 4/3 metal layers
- High density layout structure and small area design
- Flexible geometry optimization for aspect ratio requirement
- Provide power trunk with ring/ringless type instance macro
- Provide built-in options for yield/performance optimization
- Support BIST integration
- Support repaired system solution
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | BCD+ | — |
Specifications
Identity
Videos
Files
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Provider
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Frequently asked questions about SRAM IP cores
What is Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)?
Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD) is a SRAM IP core from M31 Technology Corp. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.