Overview
The IntelliProp SATA Bridge Platform is an extensible IP Core which encompasses a SATA Device core, a SATA Host core, along with an embedded processor to handle bridging between these cores including system management interfaces outside of SATA scope. The bridging interface allows for data and command manipulation along with non-host initiated command generation and processing to the attached SATA device. The negotiated transfer rate of each SATA connection is independent of the other SATA connections allowing SATA 1.5Gb/s, SATA 3Gb/s, and SATA 6Gb/s hosts and devices to communicate at their maximum rates, or lower rates to minimize power consumption.
The IPP-SA143A-BR is designed to be connected to a SATA-compliant device and SATA-compliant host PC to send and receive Out of Band (OOB) signals, primitives and SATA Frame Information Structures (FIS). The SATA ADCI Core and SATA AHCI Core of the SATA Bridge Platform interface to the system via memory mapped register sets for command and data control by the processor subsystem and DMA engines for data movement. This allows for efficient data movement between a data buffer or system-attached FIFOs and the SATA Cores.
Learn more about SATA Controller IP core
Many times we are not aware of very useful EDA tool options which are already available. Even if such options are very well documented, we don't look at them and try them. But some options are very useful and if you know them, it makes job of design engineer and/or verification engineer very easy. Here, I am going to talk about one very powerful and useful VSIM option of QuestaSim. It is VCDSTIM option of VSIM.
The paper describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM model for high speed simulation, early software development and early test-bench creation.
Oftentimes, in order to save on the cost of IP, a company will select an encrypted netlist as the deliverable instead of the RTL source code. This is especially common among companies looking to develop in FPGA devices where they can often get the necessary IP from their FPGA vendor.
To support High Definition Television (HDTV) application, the System on Chip (SoC) presented in this paper has to support multiple and concurrent internal processes. Most of these operations read data from memory, process them and store the resulting data into memory. Each functional unit of the system is responsible for a specific data processing, but all the data are stored in the same shared external memories.
Eric Esteve
Eric Esteve
