GF L12LLP 12nm Clock Generator PLL - 250MHz-1250MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- GlobalFoundries
- 12nm
- LP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
GF L12LLP 12nm Clock Generator PLL - 250MHz-1250MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L12LLP 12nm Clock Generator PLL - 500MHz-2500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
NVM OTP in Dongbu (180nm, 150nm, 110nm)
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in stand…
MIPI UniPro IP for reliable, high-performance and low power link between devices in mobile devices
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
MIPI I3C controller delivers high bandwidth and scalability for integration of multiple sensors
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB 3.0 femtoPHY in SMIC (28nm)
The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a physical (PHY) layer IP solution for low-power mobile an…
4Kx8 Bits OTP (One-Time Programmable) IP, VIS 0.15µm 1.8V BCD Process
The AT4K8V150BCD0AA is organized as a 4K-bits by 8 one-time programmable.
4Kx8 Bits OTP (One-Time Programmable) IP, GF 22nm FDX 0.8V/1.8V Process
The AT4K8G22FDX0AA is organized as a 4K-bits by 8 one-time programmable memory.
64X1 Bits OTP (One-Time Programmable) IP, GF 22nm FDX 0.8V/1.8V Process
The AT64X1G22GN0AA is organized as a 64-bit by 1 one-time programmable (OTP).
USB is a generic interface in the modern days to connect to various high speed data peripherals.
10-bit 1-channel constant power DAC
10-bit Constant power DAC employs a current steering DAC architecture with control loop, which adjusts DAC input code to keep pow…