Overview
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interface to mass storage. The complete, integrated solution is silicon-proven and includes a comprehensive suite of configurable digital controllers, high-speed mixed-
signal PHYs, and verification IP. By providing a complete solution from a single IP vendor, Synopsys lowers integration risk by ensuring that all the IP functions work together seamlessly. Synopsys IP for SATA provides designers with a high-performance IP solution that is extremely low in power, area, and latency. The IP has gone through extensive in-house and third-party interoperability testing with products shipping in volume production. As a leading supplier of SATA IP, Synopsys is focused on delivering high-quality IP. The strict quality measures, combined with an expert technical support team, enable designers to accelerate time-to-market and reduce integration risk for next-generation mass storage applications.
Learn more about SATA Controller IP core
Many chip designers use IP to improve their productivity, but unfortunately not all IP is created equal. Ed Bard, senior director of marketing, IP, and Ralph Morgan, vice president of engineering, IP, both of Synopsys, suggest that to separate the good from the bad, design teams must exercise proper due diligence when selecting IP.
Model authoring kits (MAKs) enable the rapid development of transaction-level models, TLMs, of a given functionality or protocol. MAKs include base functionalities that are common to all models independent of the RTL implementation in a well-structured way, allowing for maximum reuse. The DesignWare System-Level Library provides MAKs for UART and USB. Taking the example of a USB 2.0 EHCI controller model using MAKs, this paper explains the significant design time reduction that can be achieved.
This paper analyzes the root causes of escalating software development effort. It will highlight software driver development, specifically for traditional intellectual property (IP) models like USB, PCI-e, SATA and DDR, as a key factor in time-to-market results for combined hardware/software products. The paper will outline how higher abstraction layers of the hardware allow some areas of software development (i.e., drivers, middleware and OS’s) to become largely independent of the target hardware architecture.
In this paper, we will discuss how to select a third party IP vendor, how to verify third party IP, and some of the gotcha's when integrating third party IP, with a special focus on the SerDes-based PHYs for PCI Express and SATA as well as PHYs for USB and DDR2. In addition, we will discuss the impact of 65 nm and 45 nm process effects on yield, we will review the advantages and disadvantages of moving to serial links, we will propose complete vertical integrated solutions, and we will present production testing techniques.
Many times we are not aware of very useful EDA tool options which are already available. Even if such options are very well documented, we don't look at them and try them. But some options are very useful and if you know them, it makes job of design engineer and/or verification engineer very easy. Here, I am going to talk about one very powerful and useful VSIM option of QuestaSim. It is VCDSTIM option of VSIM.
The paper describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM model for high speed simulation, early software development and early test-bench creation.
