Crypto Box Toolset Secure Accelerator
Compact Crypto Box IP Core for Resource-Constrained Devices FortifyIQ’s Crypto Box IP core is a compact, power-efficient cryptogr…
- Security Coprocessor
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Crypto Box Toolset Secure Accelerator
Compact Crypto Box IP Core for Resource-Constrained Devices FortifyIQ’s Crypto Box IP core is a compact, power-efficient cryptogr…
Compact and Secure Post-Quantum Signature SW Library for Resource-Constrained Devices As classical digital signature algorithms f…
Compact and Secure Post-Quantum Key Encapsulation SW Library for Resource-Constrained Devices As classical asymmetric encryption …
High-Performance Hybrid Classical and Post-Quantum Cryptography
Hybrid Classical and Post-Quantum Cryptography IP Core for Future-Proof Security FortifyIQ’s High-Performance Hybrid Cryptography…
Hybrid Classical and Post-Quantum Cryptography
Hybrid Classical and Post-Quantum Cryptography IP Core for Future-Proof Security FortifyIQ’s Hybrid Cryptography IP core combines…
Versatile Post-Quantum Cryptography IP Core for Balanced Performance, Area, and Power FortifyIQ’s Post-Quantum Cryptography IP co…
Compact and Secure Post-Quantum Signature IP Core for Resource-Constrained Devices As digital signature algorithms face obsolesce…
Compact and Secure Post-Quantum ML-KEM IP Core for Resource-Constrained Devices As quantum computing threatens traditional public…
NavIC LDPC Decoder
Small footprint trusted identity Generate unclonable 128 or 256-bit seeds with a compact, logic-based PUF that drops into any SoC.
The AVSBus Verification IP provides an effective and efficient way to verify the components interfacing with AVSBus interface of …
APV - Advanced Professional Video Codec
Professional Video, APV, CODEC is a next generation of video compression & decompression tool and key technology for prosumers wh…
High-Performance SPI Master/Slave with HyperBus™ & xSPI Support The HyperBus™ Memory Controller IP Core is a high-speed, fully co…
USB 2.0 Mass Storage Devices Design Platform
The USB 2.0 Mass Storage Design Platform is a , integrated solution, dedicated to a wide range of USB-based Mass Storage Devices.
Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
The Wi-Fi 7 (802.11be) RF transceiver IP, operating in 2.4GHz / 5GHz / 6GHz bands, is tailored for next-generation high-performan…
UFS Hardware Validation Platform (HVP)
Universal Flash Storage (UFS) is a simple, high performance, mass storage device with a serial line interface.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
1-56Gbps Serdes - 7nm (Multi-reference Clock)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Ultra Low Latency)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…