Video Processing Unit IP The VPU IP is a video processing system that is suitable for high-speed and high resolution video system…
- Video Processing
- V2.6
- Two Weeks
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Video Processing Unit IP The VPU IP is a video processing system that is suitable for high-speed and high resolution video system…
Video Processing Unit IP The VPU IP is a video processing system that is suitable for high-speed and high resolution video system…
-40 to +85 °C Temperature sensor
130GF_TS_01 is a Temperature detector with unique solution intended to continuously monitor IC temperature.
Analog to Digital Converter 8 Bit
The WEA8ADC18BICAL22G is an 8-bit Successive Approximation Analog to Digital Converter.
19 GHz to 20.25 GHz FMCW Modulator for RADAR
The WEA20SFMCWI22G is an ultra-linear FMCW modulator consisting of 3 integrated PLLs.
MACsec - Extreme-Speed Variant
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model.
AES-GCM, Extreme-Speed IP Cores for AES256-GCM Authenticated Encryption
XIP1113E is a family of extreme-speed IP cores designed for AES256-GCM ( Encryption Standard with a 256-bit key and Galois Counte…
LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M4 & M33
One of the key characteristics of Bluetooth LE Audio is the new high performing standards-based LC3 audio codec.
LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M55
One of the key characteristics of Bluetooth LE Audio is the new high performing standards-based LC3 audio codec.
Bluetooth 5.2 / 5.1 / 5.0 / 4.2 LE Host
Packetcraft Host efficiently enables Bluetooth 5.2 / 5.1 / 5.0 / 4.2 LE including LE Audio and Auracast atop embedded systems ope…
Packetcraft Host efficiently enables Bluetooth 5.3 LE Audio / Auracast atop embedded systems operating with limited CPU & memory …
Packetcraft Host efficiently enables Bluetooth 5.4 PAwR (for Electronic Shelf Labels, Automotive, Agriculture and other smart sen…
Bluetooth 5.3 LE Controller with Link Layer and optional 802.15.4 MAC
Packetcraft's Bluetooth 5.3 Low Energy Controller IP, (PC-BLE-C5.3), is a optimized, comprehensive and flexible solution for inte…
Bluetooth 5.2 / 5.1 / 5.0 / 4.2 LE Controller with Link Layer and optional 802.15.4 MAC
Packetcraft's Bluetooth 5.2 / 5.1 / 5.0 / 4.2 Low Energy Controller IP, (PC-BLE-C5.2), is a optimized, comprehensive and flexible…
Dual-issue Linux-capable RISC-V core
The A730 is a dual-issue, in-order, 64-bit application processor capable of running Linux.
25kHz 1.71-5.5V Oscillator - Low Power, ± 1% accuracy at @ 27°C after trimming - TSMC0.13µm
The CM4044hh is a low power, high-accuracy, output glitch-free, wide supply voltage range, general purpose 25kHz oscillator.
DVB-S2X Multi-Carrier Demodulator
The DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers…
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …
NCR (Network Clock Reference) is a procedure to provide the master clock (i.e.
MIPI I3C Slave v1.1 Controller IP enables efficient data flow for sensor integration.
As Sensor data rate increases, there is a necessity to have control information flowing to and from sensors at an efficient data …