DPU for Convolutional Neural Network
Xilinx, Inc.
•
HQ:
USA
The Xilinx® Deep Learning Processor Unit (DPU) is a programmable engine dedicated for convolutional neural network.
- NPU
Compare 339 Xilinx, Inc. IP Cores from 1 vendors
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Xilinx, Inc.• HQ: USA
The Xilinx LogiCORE™ IP Gamma LUT core provides an optimized hardware block for manipulating image data to match response of disp…
- Image Conversion
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Xilinx, Inc.• HQ: USA
The Xilinx LogiCORE™ IP Sensor Demosaic core provides an optimized hardware block that reconstructs sub-sampled color data called…
- Image Conversion
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Xilinx, Inc.• HQ: USA
The Xilinx® LogiCORE™ IP H.264/H.265 Video Codec Unit (VCU) core for Zynq UltraScale+ MPSoC devices is capable of performing vide…
- Video Processing
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Video Frame Buffer Read and Video Frame Buffer Write
Xilinx, Inc.• HQ: USAThe Xilinx® LogiCORE™ IP Video Frame Buffer Read and Video Frame Buffer Write cores provide high-bandwidth direct memory access b…
- Video Processing
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Xilinx, Inc.• HQ: USA
Xilinx provides simple clock generator for simulation testbench.
- Clock Generator
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Soft-Decision FEC Integrated Block
Xilinx, Inc.• HQ: USAFor many current and emerging high data rate applications such as 4G, 5G and DOCSIS3.1 Cable Access, transmission reliability is …
- Channel Coding
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Xilinx, Inc.• HQ: USA
Reset Verification IP can be used to generate reset signals in testbench.
- Debug Trace
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Zynq UltraScale+ RFSoC RF Data Converter
Xilinx, Inc.• HQ: USAThe Xilinx® Zynq® UltraScale+™ RFSoC family integrates the key subsystems required to implement a software-defined radio includin…
- ADC
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Xilinx, Inc.• HQ: USA
Thread Synthesis and Reordering attachment IP for use with random access masters to HBM IP
- SRAM
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Partial Reconfiguration Bitstream Monitor IP
Xilinx, Inc.• HQ: USAThe Partial Reconfiguration (PR) Bitstream Monitor can be used to identify partial bitstreams as they flow through the design.
- Monitoring
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Partial Reconfiguration AXI Shutdown Manager IP
Xilinx, Inc.• HQ: USAThe Partial Reconfiguration (PR) AXI Shutdown Manager can be used to make the AXI interfaces between a Reconfigurable Partition a…
- System Controller
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QDMA Subsystem for PCI Express
Xilinx, Inc.• HQ: USAThe Xilinx® LogiCORE™ QDMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with th…
- PCI Express
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Xilinx, Inc.• HQ: USA
The LPDDR3 Controller gives you the ability to design with less power and a smaller form factor while maintaining high performanc…
- LPDDR
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Xilinx, Inc.• HQ: USA
Massive memory bandwidth, the simplicity of an AXI Interface, no need for external pins HBM IP, made available for Virtex UltraSc…
- HBM
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Xilinx, Inc.• HQ: USA
The ETRNIC (Xilinx Embedded Target RDMA enabled NIC) IP is a target only implementation of RDMA over Converged Ethernet (RoCE v2)…
- Ethernet
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Xilinx, Inc.• HQ: USA
Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-c…
- Interlaken
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Xilinx, Inc.• HQ: USA
The 400G High Speed Ethernet (400G HSEC) Subsystem provides the 400G Ethernet Media Access Control (MAC) with a Physical Coding S…
- Ethernet
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Xilinx, Inc.• HQ: USA
The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with…
- Ethernet
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Xilinx, Inc.• HQ: USA
The Polar Encoder/Decoder soft IP core supports Polar encoding and decoding.
- Channel Coding