Xilinx, Inc. IP Cores

The Xilinx® Deep Learning Processor Unit (DPU) is a programmable engine dedicated for convolutional neural network.

• NPU

The Xilinx LogiCORE™ IP Gamma LUT core provides an optimized hardware block for manipulating image data to match response of disp…

• Image Conversion

The Xilinx LogiCORE™ IP Sensor Demosaic core provides an optimized hardware block that reconstructs sub-sampled color data called…

• Image Conversion

The Xilinx® LogiCORE™ IP H.264/H.265 Video Codec Unit (VCU) core for Zynq UltraScale+ MPSoC devices is capable of performing vide…

• Video Processing

The Xilinx® LogiCORE™ IP Video Frame Buffer Read and Video Frame Buffer Write cores provide high-bandwidth direct memory access b…

• Video Processing

Xilinx provides simple clock generator for simulation testbench.

• Clock Generator

For many current and emerging high data rate applications such as 4G, 5G and DOCSIS3.1 Cable Access, transmission reliability is …

• Channel Coding

Reset Verification IP can be used to generate reset signals in testbench.

• Debug Trace

The Xilinx® Zynq® UltraScale+™ RFSoC family integrates the key subsystems required to implement a software-defined radio includin…

• ADC

Thread Synthesis and Reordering attachment IP for use with random access masters to HBM IP

• SRAM

The Partial Reconfiguration (PR) Bitstream Monitor can be used to identify partial bitstreams as they flow through the design.

• Monitoring

The Partial Reconfiguration (PR) AXI Shutdown Manager can be used to make the AXI interfaces between a Reconfigurable Partition a…

• System Controller

The Xilinx® LogiCORE™ QDMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with th…

• PCI Express

The LPDDR3 Controller gives you the ability to design with less power and a smaller form factor while maintaining high performanc…

• LPDDR

Massive memory bandwidth, the simplicity of an AXI Interface, no need for external pins HBM IP, made available for Virtex UltraSc…

• HBM

The ETRNIC (Xilinx Embedded Target RDMA enabled NIC) IP is a target only implementation of RDMA over Converged Ethernet (RoCE v2)…

• Ethernet

Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-c…

• Interlaken

The 400G High Speed Ethernet (400G HSEC) Subsystem provides the 400G Ethernet Media Access Control (MAC) with a Physical Coding S…

• Ethernet

The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with…

• Ethernet

The Polar Encoder/Decoder soft IP core supports Polar encoding and decoding.

• Channel Coding