Vendor:
Altera
Category:
Video Transport
SDI II Intel® FPGA IP Core
The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duple…
Overview
The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers. The SDI II IP core supports multiple standards. These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.
|
IP Core Feature |
Description |
|---|---|
|
Transceiver data interface |
20 bit, 40 bit, and 80 bit |
|
Supported SDI standards and video formats |
Note: Not all devices support all formats, see “Device Support” below |
|
SMPTE support |
|
|
Other features |
|
Block Diagram
SDI II Intel® FPGA IP Core block diagram
What’s Included?
- Design file (encrypted source code or post-synthesis netlist)
- Simulation model for ModelSim*- Intel® FPGA Edition
- Timing and/or layout constraints
- Testbench or design example
- Documentation with revision control
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
SDI II Intel® FPGA IP Core
Vendor
Altera
Provider
Altera
HQ:
USA
Altera, an Intel Company, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation.
Our innovation of programmable logic started in 1983 in Silicon Valley. In 1984, Altera unveiled the world’s first programmable logic device capable of being programmed, erased, and reprogrammed altering the future of innovation.
Learn more about Video Transport IP core
Introduction to Embedded DisplayPort (eDP) version 1.5
Tfox
Enabling High Performance SoCs Through Multi-Die Re-use
This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.
An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)
This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed architecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.
Steps for Delivering Multimedia Over 5 GHz WLANs
Steps for Delivering Multimedia Over 5 GHz WLANs
Tutorial: The H.264 Scalable Video Codec (SVC)
The H.264 Scalable Video Codec (SVC) reduces network bandwidth, eliminates transcoding, and simplifies storage management. Here's how it works.
Frequently asked questions about Video Transport IP cores
What is SDI II Intel® FPGA IP Core?
SDI II Intel® FPGA IP Core is a Video Transport IP core from Altera listed on Semi IP Hub.
How should engineers evaluate this Video Transport?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.