Vendor: SmartDV Technologies Category: Video Transport

Camera Link HS Verification IP

CameraLink HS is the serial plus parallel communication protocol developed by AIA( Imaging Association) to support the video,imag…

Contact Provider Request Datasheet

Overview

CameraLink HS is the serial plus parallel communication protocol developed by AIA(Advanced Imaging Association) to support the video,image and other data between a source device Camera and sink device Frame Grabber. Camera Link High Speed VIP can be used to verify transmitter or Receiver device following the CamerLink HS basic protocol as defined in CameraLink HS.

Camera Link HS Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Camera Link HS Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Full Camera Link HS transmitter device and receiver device functionality.
  • Supports Transmitter and Receiver Mode.
  • Supports following message packets,
    • 7 different pulse (trigger) modes of operation
    • 32 GPIO
    • Video Message
    • Command Message
    • Acknowledge Message
    • Revision Message
  • Supports 8,10,12,14,16 bit depth.
  • Supports Color Pixel formats in both Mixed and Planar data presentations
  • Supports Ack/Nack/Resend message for hand-shaking
  • Supports Packet Interruption based on message priority.
  • Supports Packetization upto 8 Cables.
  • Supports upto 15 data lanes in each Single Cable.
  • Supports 3 Gbps data rate in M-Protocol.
  • Supports 10 Gbps data rate in X-Protocol.
  • Supports 8B/10B Encoding in M-Protocol.
  • Supports 64B/66B Encoding in X-Protocol.
  • Supports Forward Error Correction (FEC) in X-Protocol.
  • Supports packing of all the video formats supported by the Camera Link HS v1.0 specifications.
  • Supports Command Message Packet format based on GenCP v1.1 specifications
  • Supports Raw,Mono,B,G,R,BGR,BGRa,Bayer GR,Bayer RG,Bayer GB,Bayer BG color format.
  • Supports Device control register set as per Camera Link HS v1.0 specifications.
  • Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Status counters for various events on bus.
  • Callbacks in node transmitter, receiver and monitor for user processing of data.
  • Camera Link HS Verification IP comes with complete test suite to test every feature of Camera Link HS v1.0 specifications.
  • Functional coverage for complete Camera Link HS features.

Block Diagram

Camera Link HS VIP block diagram

Benefits

  • Faster testbench development and more complete verification of Cameralink High Speed designs.
  • Easy to use command interface simplifies testbench control and configuration of receiver and transmitter.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the Cameralink HS testcases.
  • Examples showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Camera Link HS VIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is Camera Link HS Verification IP?

Camera Link HS Verification IP is a Video Transport IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP