Vendor: SmartDV Technologies Category: Video Transport

G.999.1 Verification IP

The G_999_1 Verification IP is compliant with ITU-T G.999.1 specifications and verifies MAC-to-PHY interfaces of designs with a 1…

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Overview

The G_999_1 Verification IP is compliant with ITU-T G.999.1 specifications and verifies MAC-to-PHY interfaces of designs with a 1G Ethernet interface GMII/GMII TBI. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. G_999_1 Verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethenet product.

G.999.1 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

G.999.1 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Follows G.999.1 specification as defined in ITU-T standard
  • Supports fragmentation
  • Supports with and without Ethernet adaption.
  • Supports full duplex and half duplex of operation
  • Supports Pause frame generation and detection.
  • Supports all types of G_999_1 TX and RX errors insertion/detection.
    • Oversize, undersize, inrange, out of range Packet size errors
    • Missing SPD/EPD/SFD framing errors
    • SFD on wrong lane
    • CRC Error
    • Disparity error injection
    • Invalid /D/ and /K/ character injection
    • Variable preamble and IPG insertion
  • Comes with G_999_1 Tx BFM, G_999_1 Rx BFM, and G_999_1 Monitor
  • Monitor supports detection of all protocol violations.
  • Built in coverage analysis.
  • Callbacks in master and slave for various events
  • Status counters for various events in bus

Block Diagram

G.999.1 VIP block diagram

Benefits

  • Faster testbench development and more complete verification of G_999_1 designs
  • Easy to use command interface simplifies testbench control and configuration of G_999_1 TX and G_999_1 RX
  • Simplifies results analysis
  • Runs in every major simulation environment

What’s Included?

  • Complete regression suite (UNH) containing all the testcases.
  • Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
G.999.1 VIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is G.999.1 Verification IP?

G.999.1 Verification IP is a Video Transport IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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