Vendor: SmartDV Technologies Category: Video Transport

SDI Verification IP

SDI Verification IP implements the digital transmision systems as specified in Serial-Digital Interface standard for microprocess…

Overview

SDI Verification IP implements the digital transmision systems as specified in Serial-Digital Interface standard for microprocessor-based sensors. SDI Verification IP provides an smart way to verify the SDI standard data transmission and control interfaces between recorder and sensor. The SmartDV's SDI Verification IP is fully compliant with SDI-12 Version 1.4 and provides the following features.

SDI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SDI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Compliant with SDI-12 Version 1.4.
  • Supports standard, fast, and high speed operations.
  • Full SDI Recorder and Sensor functionality.
  • Monitor, Detects and notifies the testbench of all protocol and timing errors.
  • Supports all recorder commands & sensor responses specified in SDI-12 Version 1.4
  • Supports all types of error insertion/detections as given below:
    • Parity Errors
    • CRC Errors
    • Invalid response Errors
    • Response timeout Errors
  • Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
  • Status counters for various events.
  • Callbacks in recorder and sensor for various events.
  • Built in functional coverage analysis.
  • SDI Verification IP comes with complete testsuite to verify each and every feature of SDI-12 Version 1.4

Block Diagram

Benefits

  • Faster testbench development and more complete verification of SDI designs.
  • Easy to use command interface simplifies testbench control and configuration of Recorder and Sensor.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the SDI testcases.
  • Examples showing how to connect various components, and usage of Recorder,Sensor and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Serial Digital Interface VIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is SDI Verification IP?

SDI Verification IP is a Video Transport IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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