Overview
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems
The Cadence® PHY IP for PCI Express® (PCIe®) 6.0 for TSMC 5nm delivers a data rate of up to 64GTps in PAM4 mode and 32/16/8/5/2.5GTps in NRZ mode. Designed specifically for infrastructure and data center applications, the PHY features advanced long-reach equalization and clock-data-recovery capabilities to achieve exceptional performance and reliability. Optimized for low latency and low active/standby power consumption, the PHY is ideal for deployment in time-critical and power-sensitive applications in high-performance computing (HPC), artificial intelligence / machine learning (AI/ML), data communications, networking, and storage systems. Cadence PHY IP is highly versatile and scalable. The PHY can be configured to support X1, X2, X4, X8, and X16 lane widths. The embedded bifurcation capability allows multiple PCIe links of various link widths to co-exist and operate independently in the same macro. A comprehensive set of diagnostic and test features is incorporated to enable faster silicon bring-up and simplify troubleshooting. EyeSurf graphic interface provides convenient access to real-time eye scope and bit-error-rate (BER) computations to monitor the link performance during live traffic. The PHY IP is fully compliant to PCIe 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1 as well as Compute Express Link (CXL) 2.0, 1.1 specifications. It is engineered to quickly and easily integrate into any system-on-chip (SoC) design. Moreover, the PHY IP connects seamlessly to Cadence’s PCIe and CXL controllers. The integrated total solution from Cadence ensures faster time to market by reducing the development cycle and minimizing risks.
Provider
Cadence Design Systems, Inc.
HQ:
USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.
Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster.
The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements.
Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Learn more about Multi-Protocol PHY IP core
Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students for careers in hardware engineering, computer architecture, and silicon chip design.
Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.
Steven Brown
The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.