Vendor: Key ASIC Category: Multi-Protocol PHY

16Gbps SerDes IP on TSMC 12nm

As the demand for higher data rates and increased serial I/O density intensifies, the performance requirements for next-generatio…

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TSMC 12nm FFC Silicon Proven View all specifications

Overview

As the demand for higher data rates and increased serial I/O density intensifies, the performance requirements for next-generation SerDes designs become more stringent, particularly in managing area and power constraints. Multi-Gigabit/s serial transceivers are rapidly supplanted traditional parallel interfaces across numerous applications. High-speed transceivers must seamlessly support a range of data rates to accommodate new link speeds and emerging standards, all while maintaining backward compatibility with legacy systems. At elevated data rates, each component must meet rigorous performance specifications to ensure overall link integrity, especially in managing jitter and maintaining a strict bit error rate amidst challenging interconnect conditions such as channel loss, impedance discontinuities caused by packaging and connectors, and crosstalk from routing limitations in the package and motherboard.

To effectively meet these challenges, serial I/O design has advanced, incorporating increasingly sophisticated architectures and cutting-edge techniques. Key ASIC’s multi-mode transceiver IP, which integrates both the PMA and PCS layers, is specifically engineered for applications demanding low power consumption and high performance. It is highly configurable and can be efficiently integrated with user logic or SoC resources, supporting data rates ranging from 1Gbps to 16Gbps.

Key features

  • Data rate: 1–16Gbps per lane
  • Supports PCIe, SATA, USB3.1, JESD204C, XAUI, SRIO, and more
  • TX: 3-tap FFE, de-emphasis control
  • RX: CTLE, multi-tap DFE
  • Adaptive equalization, SSC, PRBS generator/checker
  • On-chip eye monitor & BIST features
  • 2x QPLL for flexible clocking
  • JTAG & APB accessible register map

Block Diagram

KAT12SERDES block diagram

Benefits

  • High-speed serial connectivity in compact area
  • Silicon-proven reliability
  • Multi-standard support for versatile applications
  • Integrated debug and monitoring functions reduce development time

What’s Included?

  • Datasheet & integration guide
  • Encrypted RTL or hard macro
  • Layout views (.LEF/.GDS)
  • Timing & power reports
  • Register map, eye diagram spec
  • Verification testbenches

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC Silicon Proven

Specifications

Identity

Part Number
KAT12SERDES
Vendor
Key ASIC

Provider

Key ASIC
HQ: Malaysia
Key ASIC was incorporated in the year 2005. In 2006, we were awarded Multimedia Super Corridor (MSC) Status by the Malaysia Digital Economy Corporation (MDEC). We started with the design of IP, ASIC, and SoC. In 2009, we were listed on the main board of KLSE. Khazanah and CIMB are our main investors. Key ASIC is not only a leading ASIC / SoC design service company, we are also a turnkey service company from spec-in to system module that focuses on AI chips, IoT, and medical applications. We are committed to providing customers with competitive SoC professional one-stop design services in terms of PPA (Performance, Power, and Area). Based in Kuala Lumpur, Malaysia with R&D Centers in Malaysia and Tai Yuen Hi-Tech Industrial Park Taiwan, Key ASIC provides ODM and OEM of ASIC design services from Specification, RTL, Netlist to silicon, as well as process migration from GDSII. Our experienced SoC designer and engineers combined with extensive manufacturing, logistics resources, and a flexible engagement model can provide Key ASIC customers with a comprehensive support system for modular ASIC innovation from IP development through prototype to production.
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Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 16Gbps SerDes IP on TSMC 12nm?

16Gbps SerDes IP on TSMC 12nm is a Multi-Protocol PHY IP core from Key ASIC listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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